STM32H533CE datasheet(8/231 Pages) STMICROELECTRONICS

8 / 231 page

List of tables

STM32H533xx

8/231

DS14539 Rev 1

List of tables

Table 1.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2.

STM32H533xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3.

STM32H533xx boot mode when TrustZone is disabled (TZEN = 0xC3) . . . . . . . . . . . . . . 24

Table 4.

STM32H533xx boot mode when TrustZone is enabled (TZEN = 0xB4). . . . . . . . . . . . . . . 24

Table 5.

ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6.

AES/SAES features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 7.

Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 8.

I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 9.

I3C peripheral controller/target features versus MIPI v1.1 . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 10.

USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 11.

SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 12.

SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 13.

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 14.

STM32H533xx pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 15.

Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 16.

Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 17.

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 18.

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 19.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 20.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 21.

Maximum allowed clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 22.

Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 23.

Operating conditions at power-up/down (regulator ON) . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 24.

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 25.

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 26.

Internal reference voltage calibration value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 27.

Typical and maximum current consumption in Run mode, code with data processing

running from flash memory, 2-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 107

Table 28.

Typical and maximum current consumption in Run mode, code with data processing

running from flash memory, 1-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 108

Table 29.

Typical and maximum current consumption in Run mode, code with data processing

running from SRAM with cache 1-way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 30.

Typical and maximum current consumption in Run mode, code with data processing

running from SRAM with cache 2-way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 31.

Typical consumption in Run mode with CoreMark running

from flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 32.

Typical consumption in Run mode with SecureMark running from

flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 33.

Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 111

Table 34.

Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 35.

Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 112

Table 36.

Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 112

Table 37.

Peripheral current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 38.

Low-power mode wake-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 39.

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 40.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 41.

4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 42.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

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