STM32H533CE datasheet(32/231 Pages) STMICROELECTRONICS

32 / 231 page

Functional overview

STM32H533xx

32/231

DS14539 Rev 1

•

RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48),

can be used to drive the USB.

•

UCPD kernel clock, derived from HSI clock. The HSI RC oscillator must be enabled

prior to the UCPD kernel clock use.

•

Auxiliary clock source: two ultra-low-power clock sources that can be used to drive

the real-time clock:

–

32.768 kHz low-speed external crystal (LSE), supporting four drive capability

modes. The LSE can also be configured in bypass mode for an external clock.

–

32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

•

Peripheral clock sources: several peripherals have their own independent clock

whatever the system clock. Three PLLs, each having three independent outputs

allowing the highest flexibility, can generate independent clocks for the ADC, USB,

SDMMC, RNG, FDCAN1, OCTOSPI.

•

Startup clock: after reset, the microcontroller restarts by default with an internal

32 MHz clock (HSI/2). The prescaler ratio and clock source can be changed by the

application program as soon as the code execution starts.

•

Clock security system (CSS): this feature can be enabled by software. If a HSE clock

failure occurs, the master clock automatically switches to HSI and a software interrupt

is generated if enabled. LSE failure can also be detected and generates an interrupt.

•

Clock-out capability:

–

MCO (microcontroller clock output): it outputs one of the internal clocks for

external use by the application.

–

LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes

(except VBAT mode).

Several prescalers allow AHB and APB frequencies configuration. The maximum frequency

of the AHB and the APB clock domains is 250 MHz.

3.12.1

RCC TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in

TrustZone security mode.

The RCC TrustZone security secures some RCC system configuration and peripheral

configuration clock from being read or modified by non-secure accesses: when a peripheral

is secure, the related peripheral clock, reset, clock source selection and clock enable during

low-power modes control bits are secure.

A peripheral is in secure state:

•

when its corresponding SEC security bit is set in the TZSC (TrustZone security

controller), for securable peripherals.

•

when a security feature of this peripheral is enabled through its dedicated bits, for

TrustZone-aware peripherals.

3.13

Clock recovery system (CRS)

The devices embed a special block that allows automatic trimming of the internal 48 MHz

oscillator to guarantee its optimal accuracy over the whole device operational range. The

trimming is based on the external synchronization signal, derived from USB SOF

signalization, from LSE oscillator, from an external signal on CRS_SYNC pin, or generated

STM32H533CE Arkusz danych(PDF) 32 Page - STMicroelectronics

STM32H533CE Arkusz danych(HTML) 32 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL