STM32H533CE datasheet(30/231 Pages) STMICROELECTRONICS

30 / 231 page

Functional overview

STM32H533xx

30/231

DS14539 Rev 1

Low-power modes

By default, the microcontroller is in Run mode after a system or a power reset. It is up to the

user to select one of the low-power modes described below:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop modes

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the CSI, the

HSI, the HSI48 and the HSE crystal oscillators are disabled. The LSE or LSI is still

running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

The system clock when exiting from Stop mode can be either HSI up to 64 MHz or CSI

(4 MHz), depending on software configuration.

•

Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The

PLL, the HSI, the CSI, the HSI48 and the HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The BOR always remains active in Standby mode.

The I/Os state during Standby mode can be retained.

After entering Standby mode, SRAMs and register contents are lost except for registers

and backup SRAM in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset,

WKUP pin event (configurable rising or falling edge), an RTC event occurs (alarm,

periodic wake-up, timestamp), or a tamper detection. The tamper detection can be

raised either due to external pins or due to an internal failure detection.

The system clock after wake-up is HSI at 32 MHz.

3.10.3

Reset mode

To improve the consumption under reset, the I/Os state under and after reset is “analog

state” (the I/O Schmitt trigger is disabled).

3.10.4

VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery or an

external super-capacitor.

The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup registers

and 2-Kbyte backup SRAM. Eight anti-tamper detection pins are available in VBAT mode.

The VBAT operation is automatically activated when VDD is not present. An internal VBAT

battery charging circuit is embedded and can be activated when VDD is present.

Note:

When the microcontroller is supplied from VBAT, neither external interrupts nor RTC

alarm/events exit the microcontroller from the VBAT operation.

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