STM32H533CE datasheet(25/231 Pages) STMICROELECTRONICS

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DS14539 Rev 1

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STM32H533xx

Functional overview

(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about

the secure status of each securable peripheral, by sharing with RCC and I/O logic.

•

TZIC: TrustZone illegal access controller

This sub-block gathers all security illegal access events in the system and generates a

secure interrupt towards NVIC.

•

MPCBB: MPCBB: block-based memory protection controller

This sub-block controls secure states of all memory blocks (512-byte pages) of the

associated SRAM. This peripheral aims at configuring the internal RAM in a TrustZone

system product having segmented SRAM with programmable-security and privileged

attributes.

The GTZC main features are:

•

Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB

•

MPCBB and TZIC accessible only with secure transactions

–

Enable illegal access events that may trigger a secure interrupt

•

Secure and non-secure access supported for privileged/non-privileged part of TZSC

•

Set of registers to define product security settings:

–

Secure/privilege regions for external memories

–

Secure/privilege access mode for securable peripherals

–

Secure/privilege access mode for securable legacy masters

3.9

TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTSR2 register.

When the TrustZone is enabled, the SAU (security attribution unit) and IDAU

(implementation defined attribution unit) define the access permissions based on secure

and non-secure state.

•

SAU: up to eight SAU configurable regions are available for security attribution.

•

IDAU: It provides a first memory partition as non-secure or non-secure callable

attributes. It is then combined with the results from the SAU security attribution and the

higher security state is selected.

Based on IDAU security attribution, the flash memory, system SRAMs and peripherals

memory space is aliased twice for secure and non-secure states. However, the external

memories space is not aliased.

3.9.1

TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or TrustZone-

aware type as follows:

•

securable: peripheral protected by an AHB/APB firewall gate controlled from TZSC to

define security properties

•

TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing

a specific TrustZone behavior such as a subset of registers being secure

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