ST7265X datasheet(62/166 Pages) STMICROELECTRONICS

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ST7265x

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Data Transfer Coprocessor (Cont’d)

When the USB interface is used, data transfer is

typically controlled by a host computer.

The ST7 core can also read from and write to the

data buffer of the DTC. Typically, the ST7 controls

the application when the USB not used (autono-

mous mode). The buffer can potentially be ac-

cessed by any one of three requestors, the ST7,

the DTC and the USB. Mastership of the buffer is

not time limited. While a master is accessing the

buffer, other requests will not be acknowleged until

the buffer is freed by the master. If several re-

quests are pending, when the buffer is free it is

granted to the source with the highest priority in

the daisy-chain (fixed by hardware), first the ST7,

secondly the USB and finally the DTC.

Note: Any access by the ST7 to the buffer requires

more cycles than either a DTC or USB access. For

performance reasons, when the USB interface is

exchanging data with the DTC, ST7 accesses

should be avoided if possible.

11.2.3 Loading the Protocol Software

The DTC must first be initialized by loading the

protocol-specific software plug-in (provided by

STMicroelectronics) into the DTC RAM. To do this:

1. Stop the DTC by clearing the RUN bit in the

DTCCR register

2. Remove the write protection by setting the

LOAD bit in the DTCCR register

3. Load the (null-terminated) software plug-in in

the DTC RAM.

4. Restore the write protection by clearing the

LOAD bit in the DTCCR register

The DTC is then ready for operation.

11.2.4 Executing the Protocol Functions

To execute any of the software plug-in functions

follow the procedure below:

1. Clear the RUN bit to stop the DTC

2. Select the function by writing its address in the

DTCPR register (refer to the separate docu-

ment for address information).

3. Set the INIT bit in the DTCCR register to copy

the DTCPR pointer to the DTC.

4. Clear the INIT bit to return to idle state.

5. Set the RUN bit to start the DTC.

11.2.5 Changing the DTCPR pointer on the fly

As shown in Figure 39, the pointer can be changed

by writing INIT=1 while the DTC is running

(RUN=1), however if the DTC is executing an in-

ternal interrupt routine, there will be a delay until

interrupt handling is completed.

11.2.6 Low Power Modes

Figure 39. State Diagram of DTC Operations

Mode

Description

WAIT

No effect on DTC

HALT

DTC halted.

DTC

IDLE

POINTER

DTC

RUNNING

LOAD

DTC RAM

CHANGE

POINTER

CHANGE

ON-THE-FLY

INIT=0

INIT=1

LOAD=1

LOAD=0

RUN=1

RUN=0

INIT=1

INIT=0

RUN=0

INIT=1

LOAD=0

RUN=0

INIT=0

LOAD=1

RUN=1

INIT=1

LOAD=0

RUN=1

INIT=0

LOAD=0

RUN=0

INIT=0

LOAD=0

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