ST7265X datasheet(48/166 Pages) STMICROELECTRONICS

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ST7265x

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POWER SAVING MODES (Cont’d)

8.3 HALT MODE

The HALT mode is the MCU lowest power con-

sumption mode. The HALT mode is entered by ex-

ecuting the HALT instruction. The internal oscilla-

tor is then turned off, causing all internal process-

ing to be stopped, including the operation of the

on-chip peripherals.

When entering HALT mode, the I[1:0] bits in the

Condition Code Register are cleared. Thus, any of

the external interrupts (ITi or USB end suspend

mode), are allowed and if an interrupt occurs, the

CPU clock becomes active.

The MCU can exit HALT mode on reception of ei-

ther an external interrupt on ITi, an end suspend

mode interrupt coming from USB peripheral, an

SPI interrupt or a reset. The oscillator is then

turned on and a stabilization time is provided be-

fore releasing CPU operation. The stabilization

time is 512 CPU clock cycles.

After the start up delay, the CPU continues opera-

tion by servicing the interrupt which wakes it up or

by fetching the reset vector if a reset wakes it up.

Figure 34. HALT Mode Flow Chart

EXTERNAL

INTERRUPT*

RESET

HALT INSTRUCTION

FETCH RESET VECTOR

OR SERVICE INTERRUPT

DELAY

CPU CLOCK

OSCILLATOR

PERIPH. CLOCK

I1:0] BITS

SET

CPU CLOCK

OSCILLATOR

PERIPH. CLOCK

I1:0] BITS

OFF

CLEARED

OFF

Note: Before servicing an interrupt, the CC

set during the interrupt routine and cleared

when the CC register is popped.

(Refer to Figure 20 and

Figure 21)

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