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ST7265X Arkusz danych(PDF) 29 Page - STMicroelectronics |
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ST7265X Arkusz danych(HTML) 29 Page - STMicroelectronics |
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29 / 166 page  ST7265x 29/166 6.2 RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure 6.2.2: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET These sources act on the RESET pin and it is al- ways kept low during the delay phase. The RESET service routine vector is fixed at ad- dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 18: s Active Phase depending on the RESET source s Min 512 CPU clock cycle delay (see Figure 20 and Figure 21 s RESET vector fetch Figure 18. RESET Sequences VDD RUN RESET PIN EXTERNAL WATCHDOG ACTIVE PHASE VIT+(LVD) VIT-(LVD) th(RSTL)in tw(RSTL)out RUN th(RSTL)in ACTIVE WATCHDOG UNDERFLOW tw(RSTL)out RUN RUN RUN RESET RESET SOURCE SHORT EXT. RESET LVD RESET LONG EXT. RESET WATCHDOG RESET INTERNAL RESET (min 512 TCPU) VECTOR FETCH tw(RSTL)out PHASE ACTIVE PHASE ACTIVE PHASE DELAY 1 |
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