ST7265X datasheet(78/166 Pages) STMICROELECTRONICS

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ST7265x

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USB INTERFACE (Cont’d)

Bit 2= DTOG_TX

Data Toggle, for transmission

transfers.

This bit contains the required value of the toggle

bit (0=DATA0, 1=DATA1) for the next data packet.

DTOG_TX and DTOG_RX are normally updated

by hardware, on receipt of a relevant PID. They

can be also written by the user, both for testing

purposes and to force a specific (DATA0 or

DATA1) token.

Bits 1:0 = STAT_TX [1:0]

Status bits, for transmis-

sion transfers.

These bits contain the information about the end-

point status, which is listed below

Table 25. Transmission Status Encoding

These bits are written by software, but hardware

sets the STAT_TX bits to NAK when a correct

transfer (CTR=1) addressed to this endpoint has

occurred. This allows software to prepare the next

set of data to be transmitted.

Note: These bits are write protected in upload

mode (MOD[1:0] =01b in the EP2RXR register)

RECEPTION COUNTER REGISTER (CNT0RXR,

CNT1RXR)

Read/Write

Reset Value: 0000 0000 (00h)

This register contains the allocated buffer size for

endpoint 0 or 1 reception, setting the maximum

number of bytes the related endpoint can receive

with the next OUT (or SETUP for Endpoint 0)

transaction. At the end of a reception, the value of

this register is the max size decremented by the

number of bytes received (to determine the

number of bytes received, the software must sub-

tract the content of this register from the allocated

buffer size).

RECEPTION COUNTER REGISTER (CNT2RXR)

Read/Write

Reset Value: 0000 0000 (00h)

This register contains the allocated buffer size for

endpoint

reception,

setting

the

maximum

number of bytes the related endpoint can receive

with the next OUT transaction. At the end of a re-

ception, the value of this register is the maximum

size decremented by the number of bytes received

(to determine the number of bytes received, the

software must subtract the content of this register

from the allocated buffer size).

TRANSMISSION COUNTER REGISTER

(CNT0TXR, CNT1TXR)

Read/Write

Reset Value 0000 0000 (00h)

This register contains the number of bytes to be

transmitted by Endpoint 0 or 1 at the next IN token

addressed to it.

TRANSMISSION COUNTER REGISTER

(CNT2TXR)

Read/Write

Reset Value 0000 0000 (00h)

This register contains the number of bytes to be

transmitted by Endpoint 2 at the next IN token ad-

dressed to it.

STAT_TX1 STAT_TX0

Meaning

DISABLED: transmission

transfers cannot be executed.

STALL: the endpoint is stalled

and all transmission requests

result in a STALL handshake.

NAK: the endpoint is naked

and all transmission requests

result in a NAK handshake.

VALID: this endpoint is ena-

bled for transmission.

CNT4 CNT3 CNT2 CNT1 CNT0

CNT6 CNT5 CNT4 CNT3 CNT2 CNT CNT0

CNT4 CNT3 CNT2 CNT1 CNT0

CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

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