ST7265X datasheet(49/166 Pages) STMICROELECTRONICS

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ST7265x

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9 I/O PORTS

9.1 INTRODUCTION

Important note:

Please note that the I/O port configurations of this

device differ from those of the other ST7 devices.

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs

and for specific pins:

– external interrupt generation

– alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be

programmed independently as digital input (with or

without interrupt generation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers:

– Data Register (DR)

– Data Direction Register (DDR)

and one optional register:

– Option Register (OR)

Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR regis-

ters: bit X corresponding to pin X of the port. The

same correspondence is used for the DR register.

The following description takes into account the

OR register, (for specific ports which do not pro-

vide this register refer to the I/O Port Implementa-

tion section). The generic I/O block diagram is

shown in Figure 35

9.2.1 Input Modes

The input configuration is selected by clearing the

corresponding DDR register bit.

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

Different input modes can be selected by software

through the OR register.

Notes:

1. Writing the DR register modifies the latch value

but does not affect the pin status.

2. When switching from input to output mode, the

DR register has to be written first to drive the cor-

rect level on the pin as soon as the port is config-

ured as an output.

External interrupt function

When an I/O is configured as Input with Interrupt,

an event on this I/O can generate an external inter-

rupt request to the CPU.

Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently

programmable using the sensitivity bits in the Mis-

cellaneous register.

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see pinout description

and interrupt section). If several input pins are se-

lected simultaneously as interrupt source, these

are logically NANDed and inverted. For this rea-

son if one of the interrupt pins is tied low, it masks

the other ones.

In case of a floating input with interrupt configura-

tion, special care must be taken when changing

the configuration (see Figure 36).

The external interrupts are hardware interrupts,

which means that the request latch (not accessible

directly by the application) is automatically cleared

when

the

corresponding

interrupt

vector

fetched. To clear an unwanted pending interrupt

by software, the sensitivity bits in the Miscellane-

ous register must be modified.

9.2.2 Output Modes

Two different output modes can be selected by

software through the OR register: Output push-pull

and open-drain.

DR register value and output pin status:

The output configuration is selected by setting the

corresponding DDR register bit. In this case, writ-

ing the DR register applies this digital value to the

I/O pin through the latch. Reading the DR register

returns the digital value present on the external I/O

pin. Consequently even in output mode a value

written to an open drain port may differ from the

value read from the port. For example, if software

writes a ‘1’ in the latch, this value will be applied to

the pin, but the pin may stay at ‘0’ depending on

the state of the external circuitry. For this reason,

bit manipulation even using instructions like BRES

and BSET must not be used on open drain ports

as they work by reading a byte, changing a bit and

writing back a byte. A workaround for applications

requiring bit manipulation on Open Drain I/Os is

given in Section 9.2.4.

Push-pull

Open-drain

0VSS

Vss

1VDD

Floating

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