ST7265X datasheet(109/166 Pages) STMICROELECTRONICS

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11.7 I²C SINGLE MASTER BUS INTERFACE (I2C)

11.7.1 Introduction

The I2C Bus Interface serves as an interface be-

tween the microcontroller and the serial I2C bus. It

provides single master functions, and controls all

I2C bus-specific sequencing, protocol and timing.

It supports fast I²C mode (400kHz).

11.7.2 Main Features

– Parallel bus /I2C protocol converter

– Interrupt generation

– Standard I2C mode /Fast I2C mode

– 7-bit Addressing

I2C single Master Mode

– End of byte transmission flag

– Transmitter/Receiver flag

– Clock generation

11.7.3 General Description

In addition to receiving and transmitting data, this

interface converts it from serial to parallel format

and vice versa, using either an interrupt or polled

handshake. The interrupts are enabled or disabled

by software. The interface is connected to the I2C

bus by a data pin (SDAI) and by a clock pin (SCLI).

It can be connected both with a standard I2C bus

and a Fast I2C bus. This selection is made by soft-

ware.

Mode Selection

The interface can operate in the two following mo-

des:

– Master transmitter/receiver

By default, it is idle.

The interface automatically switches from idle to

master after it generates a START condition and

from master to idle after it generates a STOP con-

dition.

Communication Flow

The interface initiates a data transfer and genera-

tes the clock signal. A serial data transfer always

begins with a start condition and ends with a stop

condition. Both start and stop conditions are gene-

rated by software.

Data and addresses are transferred as 8-bit bytes,

MSB first. The first byte following the start condi-

tion is the address byte.

A 9th clock pulse follows the 8 clock cycles of a

byte transfer, during which the receiver must send

an acknowledge bit to the transmitter. Refer to Fig-

ure 66.

Figure 66. I2C BUS Protocol

SCL

SDA

MSB

ACK

STOP

START

CONDITION

VR02119B

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