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ST7265X Arkusz danych(PDF) 154 Page - STMicroelectronics |
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ST7265X Arkusz danych(HTML) 154 Page - STMicroelectronics |
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154 / 166 page  ST7265x 154/166 13.12 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Figure 104. Typical Application with ADC Notes: 1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide- lines and are not tested. 2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS . 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k Ω). Data based on characterization results, not tested in production. 4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then always valid. Symbol Parameter Conditions Min Typ 1) Max Unit fADC ADC clock frequency 4 MHz VAIN Conversion range voltage 2) VSSA VDDA V RAIN External input resistor 10 3) k Ω CADC Internal sample and hold capacitor 6 pF tSTAB Stabilization time after ADC enable fCPU=8MHz, fADC=2MHz 0 4) µs tADC Conversion time (Sample+Hold) 6 - Sample capacitor loading time - Hold conversion time 4 8 1/fADC AINx ST72XXX CIO ~2pF VDD IL ±1 µA VT 0.6V VT 0.6V VAIN RAIN VDDA VSSA 0.1 µF VDD ADC |
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