STLC1502 datasheet(69/81 Pages) STMICROELECTRONICS

69 / 81 page

69/81

STLC1502

Figure 15: Interrupt Block

10.3 Clock Distribution

•

The PCM block works at 2.048Mhz clock and it is a fully synchronous design at that frequency. No

gated clock, no latches are used.

•

The design is able to support also higher PCM hierarchies such as 4.096Mhz and 8.196Mhz.

•

The D950 interface works as a clock stage decoupling block. It can be accessed externally at 66Mhz,

while internally it works at 2.048Mhz.

10.4 Reset Distribution and Configuration

•

The PCM block has an explicit active low reset pin controlled by ARM.

•

A software reset is implemented in the PCM_CONFIGURATION register at the address 0x0002.

•

In the PCM_CONFIGURATION register there is also a bit that configures the FPGA itself as linear or

PCM coding.

10.5 Data Flow Management

Per each direction the PCM block contains a double buffer used to store and forward the voice samples. This

has to be big enough to store all (four) voice samples coming (and going) from (to) the SLICs contained in one

PCM frame. Actually the number of bits per voice channel per PCM frame is 8 in case of PCM coding (A low or

u low) and 16 in case of linear coding. Other bits are used to provide information about the number of the logic

channel the frame is associated with.

So, it is necessary to have two memory banks per direction.

For example, in the upstream direction (from the codec to the D950), one bank is used to store the incoming

voice samples (on-line bank) and the other used to keep the voice samples received in the previous PCM frame

(off-line bank) while they are read by the D950. This mechanism is needed because the PCM flow is synchro-

PCM_INTERRUPT_MASK

Enable

D950 ITR3

Other Interrupt Bit Slices

PCM_INTERRUPT

PCM_INTERRUPT_ROW

Interrupt Source

Interrupt Pending

STLC1502 Arkusz danych(PDF) 69 Page - STMicroelectronics