STLC1502 datasheet(17/81 Pages) STMICROELECTRONICS

17 / 81 page

17/81

STLC1502

The EDM block includes a decoder in order to generate proper CS to the external device. In particular this de-

coder will work on bits 25 and 26 of internal ARM address bus.

EDM decoding scheme

•

Every CS space can be programmed through internal register in order to configure the EDM to work

with the proper external device

•

The DRAM Controller has nine registers, the configuration register, four bank registers and four

SDRAM configuration registers. The registers are accesses via the APB bus. The register data path

is 16 bits wide.

6.3.1 EDM Register Map [0x0C580000]

•

The base address of the EDM register is 0x0C580000

EDM_RAS

OUT

SDRAM RAS signal. Not used with EDO.

EDM_CAS

OUT

SDRAM CAS signal. Not used with EDO

OEN

OUT

SRAM

Output

Enable.

Not

used

with

SDRAM

EDM_WE

OUT

DRAM Write Enable

EDM_BS(3:0)

OUT

SDRAM byte strobe. CAS when EDO memo-

ries are used

EDM_A(21::0)

OUT

DRAM address lines, only 14 lines are

driven.. Lines.21:14 are driven by static

memory controller

EDM_D(31:0)

INOUT

DRAM data lines, shared with static memory

controller lines.

EDM

Decoder

EDM_A(13:0)

Address

Name

R/W

Notes

EDMBase +

0x00

MB1Config

R/W

Memory Bank 1 Configuration Register

EDMBase +

0x04

MB2Config

R/W

Memory Bank 2 Configuration Register

NAME

Signal type

Description

STLC1502 Arkusz danych(PDF) 17 Page - STMicroelectronics

STLC1502 Arkusz danych(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Arkusz danych Pobierz

Link URL