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STLC1502 Arkusz danych(PDF) 43 Page - STMicroelectronics |
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STLC1502 Arkusz danych(HTML) 43 Page - STMicroelectronics |
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43 / 81 page ![]() 43/81 STLC1502 7.5.4 Collision management Collision is defined as a write of the DR register while the internal serial clock (SCK) is in the process of transfer. The WCOL bit in the SR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence: 1-Read SR 2-Read DR 7.5.5 SPI register map [0x0C280000] The base address of the Remap & Pause register is 0x0C280000. |
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