STLC5460 datasheet(27/54 Pages) STMICROELECTRONICS

27 / 54 page

BUSY

Busy.

The memories cannot be accessed if this bit is at ”1”. In this case, a new access of

three memory access registers [Command Register (CMD); source Register (SRC)

and Destination Register (DST)] will be ignored. If the microprocessor has Twait

cycles (working with DTACK or READY), the test BUSY is not necessary.

PRSR

Pseudo Random Sequence Recovered.

When the PRS analyser is validated, PRS bit is put to ”one” if the synchronization is

performed.

MONR

Monitor Channel Receive.

When this bit is at ”1”, a byte has been received from one or more Monitor channel.

The microprocessor must read the Receive Monitor Status Register (RMS)

MONT

Monitor Channel Transmit.

When this bit is at ”1”, one (or more) channel is transmitting a message and is

ready to transmit a new byte of this message.The microprocessor must read the

Transmit Monitor Status Register (TMS).

When this bit is at ”0”, each channel is IDLE, and is ready to transmit a new message.

CIR

Command/Indicate Receive.

When this bit is at ”1”, a new primitive has been received from one or more

Command/Indicate channel. The microprocessor can read the Receive

Command/Indicate Status Register (RCIS).

EXT

Extract Status.

This bit is put ot ”1” when a new byte has been written in the extract registers A or/

and B, when it is at ”1” the Extract Registers can be read during 120 microseconds

before changing. The bit is reset after the reading of the STATUS Register.

INS

Insert Status.

When this bit is at ”0”, the Insert Register A or/and B can be written during 120

µs

before the next transmission. After the Insert Registers have been written the bit goes

automatically to ”1”, the bit is put at ”0” after the reading of the status register.

INSERTION A REGISTER (INS A)

IA7

IA6

IA5

IA4

IA3

IA2

IA1

IA0

After Reset 00 (H)

IA 0/7

This register contains the data to insert during the Time Slot (s) of the output

multiplex(es) indicated by the Command Memory. After transferring INS, interrupt is

generated

INSERTION B REGISTER (INS B)

IB7

IB6

IB5

IB4

IB3

IB2

IB1

IB0

After Reset 00 (H)

IB 0/7

This register contains the data to insert during the Time Slot(s) of the output

multiplex(es) indicated by the Command Memory. After transferring, INS interrupt is

generated.

STLC5460

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