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STLC5460 Arkusz danych(PDF) 6 Page - STMicroelectronics |
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STLC5460 Arkusz danych(HTML) 6 Page - STMicroelectronics |
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6 / 54 page ![]() First bit of the frame First bit of the frame First bit of the frame First bit of the frame DEL=1 DCL=1 PFSP=1 DEL=0 DCL=1 DCL=1 PFSP=0 DEL=0 DCL=1 Mode not delayed: DEL=1 PFS PFS PFS PFS PDC PDC PDC PDC PFSP=0 PFSP=1 Mode delayed: Clocks received by the circuit Figure 1: PCM Interface. Alignment in double clock mode. STLC5460 6/54 |
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