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STLC5460 Arkusz danych(PDF) 37 Page - STMicroelectronics |
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STLC5460 Arkusz danych(HTML) 37 Page - STMicroelectronics |
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37 / 54 page ![]() DCL delivered by DIN 0/1 FSC delivered by DOUT 0/1 Bit0, Time Slot 0 the LCIC the LCIC Bit7, Time Slot 31 t1 t5 t6 t7 t8 t2 PDC received by the LCIC t3 t4 The four Multiplex Configuration Registers are at zero (no delay between FSC and Multiplexes) CLOCK TIMING TDM synchronization Clocks delivered by the LCIC tx Parameter T min. T typ. T max. Unit t1 Clock Period if 4096KHz Clock Period if 2048KHz Id PDC 244 488 Id PDC ns ns t2 Delay between PDC and DCL (30pF) 5 30 ns t3 Delay between DCL and rising edge FSC (30pF) 30 ns t4 Delay between DCL and falling edge FSC (30pF) 30 ns t5 Duration FSC 488 ns t6 DCL to data 50pF DCL to data 100pF 50 100 ns ns t7 Set up time data/DCL 20 ns t8 Hold time data/DCL 20 ns STLC5460 37/54 |
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