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Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

4.1.28

ESMRAMC—Extended System Management RAM Control

(D0:F0)

PCI Device:

Address Offset:

9Eh

Default Value:

00h

Access:

R/W/L, RO

Size:

8 bits

The Extended SMRAM register controls the configuration of Extended SMRAM space. The

Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory

space that is above 1 MB.

Bit

Access &

Default

Description

R/W/L

Enable High SMRAM (H_SMRAME): This bit controls the SMM memory space

location (i.e., above 1 MB or below 1 MB). When G_SMRAME is 1 and H_SMRAME

is 1, the high SMRAM memory space is enabled. SMRAM accesses within the range

0FEDA0000h to 0FEDBFFFFh are remapped to DRAM addresses within the range

000A0000h to 000BFFFFh. Once D_LCK has been set, this bit becomes read only.

R/W/C

Invalid SMRAM Access (E_SMERR): This bit is set when the processor has

accessed the defined memory ranges in Extended SMRAM (High Memory and T-

segment) while not in SMM space and with the D-OPEN bit = 0. It is software’s

responsibility to clear this bit. The software must write a 1 to this bit to clear it.

SMRAM Cacheable (SM_CACHE): This bit is forced to 1 by the (G)MCH .

L1 Cache Enable for SMRAM (SM_L1): This bit is forced to 1 by the (G)MCH.

L2 Cache Enable for SMRAM (SM_L2): This bit is forced to 1 by the (G)MCH.

2:1

R/W/L

00b

TSEG Size (TSEG_SZ): This field selects the size of the TSEG memory block if

enabled. Memory from the top of DRAM space is partitioned away so that it may

only be accessed by the processor interface and only then when the SMM bit is set

in the request packet. Non-SMM accesses to this memory region are sent to the

DMI when the TSEG memory block is enabled.

00 = 1-MB Tseg. (TOLUD – Graphics Stolen Memory Size – 1M) to (TOLUD –

Graphics Stolen Memory Size).

01 = 2-MB Tseg (TOLUD – Graphics Stolen Memory Size – 2M) to (TOLUD –

Graphics Stolen Memory Size).

10 = 8-MB Tseg (TOLUD – Graphics Stolen Memory Size – 8M) to (TOLUD –

Graphics Stolen Memory Size).

11 = Reserved.

Once D_LCK has been set, these bits become read only.

NOTE: References to Graphics Stolen Memory only apply to the

82915G/82915GV/82915GL/82910GL GMCH only.

R/W/L

TSEG Enable (T_EN): This bit Enables SMRAM memory for Extended SMRAM

space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to

appear in the appropriate physical address space. Note that once D_LCK is set, this

bit becomes read only.

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