910GL datasheet(59/426 Pages) INTEL

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3.3.3

Primary PCI and Downstream Configuration Mechanism

If the Bus Number in the CONFIG_ADDRESS is non-zero, and falls outside the range claimed

by the Host-PCI Express bridge (not between upper bound in device’s Subordinate Bus Number

generate a Type 1 DMI Configuration Cycle. This DMI configuration cycle will be sent over the

DMI.

If the cycle is forwarded to the Intel ICH6 via the DMI, the Intel ICH6 compares the non-zero

Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its PCI-

to-PCI bridges to determine if the configuration cycle is meant for ICH6 PCI Express ports one of

the Intel ICH6’s devices, the DMI, or a downstream PCI bus.

Figure 3-3. DMI Type 0 Configuration Address Translation

24 23

16 15

11 10

8 7

2 1

DMI_Typ0_Config

Reserved

Bus Number

Device

Number

Function

Double

Word

24 23

16 15

11 10

Reserved

Bus Number

Device

Number

Function

Double

Word

OCFBh

DMI Type 0 Configuration Address Extension

Configuration Address

OCFAh

OCF9h

OCF8h

Figure 3-4. DMI Type 1 Configuration Address Translation

24 23

16 15

11 10

DMI_Typ1_Config

Reserved

Bus Number

Device

Number

Function

Double

Word

24 23

16 15

11 10

Reserved

Bus Number

Device

Number

Function

Double

Word

OCFBh

DMI Type 1 Configuration Address Extension

Configuration Address

OCFAh

OCF9h

OCF8h

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