910GL datasheet(57/426 Pages) INTEL

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Figure 3-2. Register Organization (Representative of the Intel

® 82915G GMCH)

000h

VC1 (Isochronous) Port

Arbitration Controls

Reg_Org_82915G

(G)MCH-ICH6 Serial Interface

(DMI) Controls:

Analog Controls Error

Reporting Controls VC Control

(Incl. VCp)

PCI Express* Egress Port

(RCRB)

DMI Root Complex Register

Block (RCRB)

Accessed only by PCI

Express enhanced access

mechanism. 4KB block

allocated for each potential

device in root hierarchy.

PCI Express Address Range

Device 2 Range

Device 1 Range

Device 0 Range

Thermal Sensor PSB Analog

Controls (Rcomp+)

CH 0/1 Analog Controls

CH 0/1 Timing Controls

Ch 0/1 Throttling

Ch 0/1 Oranization Arviter

Controls

Device 0 MMIO Registers:

(G)MCH Control

Unused

Device 0 Configuration

Registers

Device Level Controls, PAM

EPBAR

DMI BAR

PCIEXBAR

MCHBAR

000h

0FFh

FFFh

PCI Express x16 Controls:

Analog Controls

Error Reporting Controls

VC Controls

Hot Plug/Slot Controls

Device 1 Configuration

Registers: PCI Express X16

Device Level Controls

000h

0FFh

FFFh

Unused

Device 2 Configuration

Registers: Internal Graphics

Mirror of bits needed by

graphics driver graphics

thermal controls

000h

0FFh

FFFh

Note: Diagram not to scale

0000h

3FFFh

0000 0000h

0FFF FFFFh

000h

FFFh

NOTES:

Very high level representation. Many details omitted.

Inter graphics memory mapped registers are not shown.

Only Device 1 use PCI Express extended configuration space.

Device 0 and Device 2 use only standard PCI configuration space.

Hex numbers represent address range size and not actual locations.

Table 3-1. Device Number Assignment for Internal (G)MCH Devices

(G)MCH Function

Device#

Host Bridge / DRAM Controller

Device 0

Host-to-PCI Express* Bridge (virtual P2P) (Intel

® 82915G/82915P/82915PL

(G)MCH only)

Device 1

Internal Graphics Control (82915G/82915GV/82915GL/82910GL GMCH

only)

Device 2

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