910GL datasheet(35/426 Pages) INTEL

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Signal Description

Datasheet

2.1

Host Interface Signals

Note:

Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination

voltage of the Host Bus (VTT).

Signal Name

Type

Description

HADS#

I/O

GTL+

Address Strobe: The processor bus owner asserts HADS# to indicate the

first of two cycles of a request phase. The (G)MCH can assert this signal for

snoop cycles and interrupt messages.

HBNR#

I/O

GTL+

Block Next Request: This signal is used to block the current request bus

owner from issuing new requests. This signal is used to dynamically control

the processor bus pipeline depth.

HBPRI#

GTL+

Priority Agent Bus Request: The (G)MCH is the only Priority Agent on the

processor bus. It asserts this signal to obtain the ownership of the address

bus. This signal has priority over symmetric bus requests and will cause the

current symmetric owner to stop issuing new transactions unless the

HLOCK# signal was asserted.

HBREQ0#

I/O

GTL+

Bus Request 0: The (G)MCH pulls the processor’s bus HBREQ0# signal

low during HCPURST#. The processor samples this signal on the active-to-

inactive transition of HCPURST#. The minimum setup time for this signal is

4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is

20 HCLKs. HBREQ0# should be tristated after the hold time requirement

has been satisfied.

HCPURST#

GTL+

CPU Reset: The HCPURST# pin is an output from the (G)MCH. The

(G)MCH asserts HCPURST# while RSTIN# is asserted and for

approximately 1 ms after RSTIN# is de-asserted. The HCPURST# allows

the processors to begin execution in a known state.

Note that the Intel

® ICH6 must provide processor frequency select strap set-

up and hold times around HCPURST#. This requires strict synchronization

between (G)MCH HCPURST# de-assertion and the Intel® ICH6 driving the

straps.

HDBSY#

I/O

GTL+

Data Bus Busy: This signal is used by the data bus owner to hold the data

bus for transfers requiring more than one cycle.

HDEFER#

GTL+

Defer: Signals that the (G)MCH will terminate the transaction currently

being snooped with either a deferred response or with a retry response.

HDINV[3:0]#

I/O

GTL+

Dynamic Bus Inversion: Driven along with the HD[63:0] signals. Indicates

if the associated signals are inverted or not. HDINV[3:0]# are asserted such

that the number of data bits driven electrically low (low voltage) within the

corresponding 16 bit group never exceeds 8.

HDINVx#

Data Bits

HDINV3#

HD[63:48]

HDINV2#

HD[47:32]

HDINV1#

HD[31:16]

HDINV0#

HD[15:0]

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