QG80331M500 datasheet(65/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Documentation Changes

Affected Docs: Intel® 80331 I/O Processor Developer’s Manual

Table 237.

DDR SDRAM Control Register 1 - SDCR1

Bit

Default

Description

DQS# Disable: Controls the behavior of the strobes as well as the configuration of the DIMM.

0 = DQS# Enabled for Differential operation, EMRS bit 10 will be programmed as zero.

1 = DQS# Disabled for Singled-ended operation, EMRS bit 10 will be programmed as one.

30:28

0002

RTCMD: Read-to-Command (non-Read) turnaround period in MCLK periods.

•

010 = 2 MCLK periods (DDR-I Type only)

•

011 = 3 MCLK periods (DDR-II Type only)

all other values reserved

27:24

WTCMD: Write-to-Command (non-Read) turnaround period in MCLK periods.

Equation 10: WTCMD = tCAS + tWR + tREG

where tREG = 1 for registered DIMM and 0 for unbuffered DIMM, tCAS and tWR are from SPD.

Reserved

22:20

0002

RTW: Read-to-Write turnaround period in MCLK periods.

Equation 11: RTW = tCAS + (BL/2) + tREG + (tEDP-1) = tCAS + tREG + 3

where tREG = 1 for registered DIMM and 0 for unbuffered DIMM, BL=4, tCAS is from SPD, and EDP=2.

NOTE: a programmed value of 0002 represents a decimal value of eight (8).

19:17

0002

Reserved

16:12

0 00002

RFC: Refresh-to-Active and Refresh-to-Refresh period in MCLK periods

Equation 12: RFC = tRFC - 1

where tRFC is from SPD

11:09

0002

WR: Write Recovery time in MCLK periods.

•

000 = 0 - for DDR333

•

010 = 3 - for DDR-II 400 (encoding per JEDEC spec)

all other values reserved

08:04

0 00002

RC: Active-to-Active and Active-to-Refresh period in MCLK periods.

Equation 13: RC = tRC - 1

where tRC is from SPD

03:00

WTRD: Write-to-Read turnaround period in MCLK periods.

Equation 14: WTRD = tCAS + tWTR + tREG

where tREG = 1 for registered DIMM and 0 for unbuffered DIMM, tCAS and tWTR are from SPD.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Intel XScale® core Local Bus Address

FFFF E508H

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