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QG80331M500 Arkusz danych(PDF) 12 Page - Intel Corporation |
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QG80331M500 Arkusz danych(HTML) 12 Page - Intel Corporation |
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12 / 67 page ![]() 12 Specification Update Intel® 80331 I/O Processor Summary Table of Changes 53 XX XXX X 38 No Fix PCI-to-PCI read flow-through with destination TRDY# stalls can cause data corruption 54 XX XX 38 Fixed S_PCIXCAP PCI mode threshold is too high 55 XX XXX X 39 No Fix No support for burst I/O and configuration read/writes 56 XX XXX X 39 No Fix Read flow through hangs due to disconnect without data at a buffer boundary. 57 XX XXX X 39 No Fix P_SERR# not asserted for parity error on AD[63:32] 58 XX XXX X 39 No Fix Bus Interface Unit (BIU) claims DAC addresses in the range of the Memory Mapped Registers (MMR 59 XX XXX X 40 No Fix PCIX-to-PCI Memory Read issued as 32-bit, then retried as 64-bit 60 XX XXX X 41 No Fix Tc1(min) of the PCI-X clock observed to be marginally less than the requirement specified for the PCI-X (Mode 1, class1) clock jitter. 61 XX XXX X 41 No Fix I2C Control Register reset bit does not function 62 X 41 Fixed Internal Clock Misalignment Can Cause Processor Hang. 63 XX XXX X 41 No Fix Spurious DMA0 End-Of-Transfer Interrupt Non-Core Errata (Sheet 3 of 3) No. Steppings Page Status Errata A-1 B-0 C-0 C-1 D-0 D-1 |
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