QG80331M500 datasheet(29/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Non-Core Errata

37.

Intel XScale® Core lockup condition

Problem:

The Intel XScale® core fetches code and data through an internal switch called the Bus Interface

Unit (BIU), which manages traffic in two directions; a general path to the Flash and PCI-X

interfaces (as well as internal units) and a private path to DDR memory controller. There is a

boundary condition for returning data, specifically for code fetches from Flash or host memory

colliding with private DDR read data. At the wrong clock alignment, the BIU corrupts the

returning code with the DDR data. This results in arbitrary code returned to the core, resulting in

lockup or other unpredictable core behavior. The following describes one scenario of how this

condition can occur:

• The Intel XScale® core fetches an instruction cache line, which is executed through the

internal bus to the Flash interface unit and out to Flash memory.

• While this is happening, the Intel XScale® core is scrubbing the DDR clean with a series of

data transactions through a second private path, directly to the DDR Memory Controller.

These data transactions are a series of cache line writes to DDR and reads from DDR.

• The original instruction fetch is returned from the Flash interface unit back to the core with the

critical instruction first (critical word first).

• One clock after the instruction cache line is being returned to the Intel XScale® core, one of

the data transactions returns from the DDR memory controller.

• The BIU switches to handle the higher priority DDR return.

• The instruction cache line that was being returned from the Flash interface is only partially

returned to the Intel XScale® core (five of the eight instructions).

• The data cache line from the DDR memory controller is then returned to the Intel XScale®

core in its entirety.

• The Intel XScale® core then starts executing the instructions that were fetched in the cache

line (since the critical instruction was returned first, the core can continue).

• The five instructions that were returned are executed by the Intel XScale® core and the core

then stalls waiting for the sixth, seventh and eighth instruction to be returned from the initial

cache line fill.

• The BIU continues to return any outstanding transactions unaware that the instruction cache

fetch was not fully returned.

Note:

1) The case where this happens is where the core memory port is enabled and there is a cache line

fill (instruction or data) that executes through the internal bus (Flash/PCI/etc., transactions, not

DDR transactions) and any size fetch to DDR through the direct port to DDR memory controller.

The timing has to be such that the cache line fill from the internal bus must beat the DDR return by

1 clock cycle.

2) The scenario given above is just one example of what excites this condition and is by no means

the only scenario that excites this condition.

Implication:

This results in a lockup or other unpredictable core behavior.

Workaround:

For A-x and B-0 silicon the only reliable workaround is for software to turn off the core to the

DDR Memory Controller port, redirecting DDR accesses through the Internal Bus interface with

other transactions. This prevents the core lockup condition but at a cost to performance.

Status:

Fixed. Fixed in C-0 stepping. See the Table , “Summary Table of Changes” on page 9.

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