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AM79C970AVCW Arkusz danych(PDF) 38 Page - Advanced Micro Devices |
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AM79C970AVCW Arkusz danych(HTML) 38 Page - Advanced Micro Devices |
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38 / 219 page ![]() AMD P R E L I M I N A R Y 38 Am79C970A When the host is not yet ready when the PCnet-PCI II controller asserts TRDY, the device will wait for the host to assert IRDY. When the host asserts IRDY and FRAME is still asserted, the PCnet-PCI II controller will finish the first data phase by deasserting TRDY one clock later. At the same time, it will assert STOP to signal a disconnect to the host. STOP will stay asserted until the host removes FRAME. 19436A-11 FRAME CLK AD IRDY TRDY C/ BE DEVSEL STOP 1 23456 PAR BE PAR PAR BE DATA 1st DATA Figure 8. Disconnect Of Slave Burst Transfer—Host Inserts Wait States |
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