AM79C970AVCW datasheet(56/219 Pages) AMD

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P R E L I M I N A R Y

Am79C970A

Initialization Block DMA Transfers

During execution of the PCnet-PCI II controller bus

master initialization procedure, the PCnet-PCI II con-

troller microcode will repeatedly request DMA transfers

from the BIU. During each of these initialization block

DMA transfers, the BIU will perform two data transfer cy-

cles reading one DWord per transfer and then it will re-

linquish the bus. When SSIZE32 (BCR20, bit 8) is set to

ONE (i.e. the initialization block is organized as 32-bit

software structures), there are 7 DWords to transfer dur-

ing the bus master initialization procedure, so four bus

mastership periods are needed in order to complete the

initialization sequence. Note that the last DWord trans-

fer of the last bus mastership period of the initialization

sequence accesses an unneeded location. Data from

this transfer is discarded internally. When SSIZE32 is

cleared to ZERO (i.e. the initialization block is

organized as 16-bit software structures), then three bus

mastership periods are needed to complete the

initialization sequence.

The PCnet-PCI II controller supports two transfer

modes for reading the initialization block: non-burst and

burst mode; with burst mode being the preferred mode

when the PCnet-PCI II controller is used in a PCI

bus application.

When BREADE is cleared to ZERO (BCR18, bit 6), all

initialization block read transfers will be executed in

non-burst mode. There is a new address phase for

every data phase.

FRAME will be dropped between

the two transfers. The two phases within a bus

mastership period will have addresses of ascending

contiguous order.

19436A-27

FRAME

CLK

IRDY

TRDY

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

IADDi

0000

0110

PAR

DATA

IADDi+4

0000

0110

PAR

2345678

Figure 24. Initialization Block Read In Non-Burst Mode

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