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AM79C970AVCW Arkusz danych(PDF) 49 Page - Advanced Micro Devices |
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AM79C970AVCW Arkusz danych(HTML) 49 Page - Advanced Micro Devices |
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49 / 219 page ![]() P R E L I M I N A R Y AMD 49 Am79C970A Disconnect Without Data Transfer The figure below shows a target disconnect sequence during which no data is transferred. STOP is asserted on clock 4 without TRDY being asserted at the same time. The PCnet-PCI II controller terminates the access with the deassertion of FRAME on clock 5 and of IRDY one clock cycle later. It finally releases the bus on clock 6. The PCnet-PCI II controller will re-request the bus after 2 clock cycles to retry the last transfer. The starting address of the new transfer will be the address of the last untransferred data. 19436A-21 FRAME CLK AD IRDY TRDY C/ BE DEVSEL REQ GNT PAR DEVSEL is sampled ADDRi 0000 0111 PAR 0111 1 2345678 10 9 STOP ADDRi DATA PAR Figure 18. Disconnect Without Data Transfer |
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