AM79C970AVCW datasheet(55/219 Pages) AMD

55 / 219 page

P R E L I M I N A R Y

AMD

Am79C970A

error as if nothing has happened. All network

activity continues.

Advanced Parity Error Handling

For all DMA cycles, the PCnet-PCI II controller provides

a second, more advanced level of parity error handling.

This mode is enabled by setting APERREN (BCR20,

bit 10) to ONE.

When APERREN is set to ONE, the BPE bits (RMD1

and TMD1, bit 23) are used to indicate parity error in

data transfers to the receive and transmit buffers. Note

that since the advanced parity error handling uses an

additional bit in the descriptor, SWSTYLE (BCR20, bits

7–0) must be set to ONE, TWO or THREE to program

the PCnet-PCI II controller to use 32-bit software

structures. The PCnet-PCI II controller will react in the

following way when a data parity error occurs:

s Initialization block read: STOP (CSR0, bit 2) is set to

ONE and causes a STOP_RESET of the device.

s Descriptor ring read: Any on-going network activity is

terminated in an orderly sequence and then STOP

(CSR0, bit 2) is set to ONE to cause a STOP_RESET

of the device.

s Descriptor ring write: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bit 2) is set to ONE to cause a STOP_RESET

of the device.

s Transmit buffer read: BPE (TMD1, bit 23) is set in the

current transmit descriptor. Any on-going network

transmission is terminated in an orderly sequence.

s Receive buffer write: BPE (RMD1, bit 23) is set in the

last receive descriptor associated with the frame.

Terminating on-going network transmission in an or-

derly sequence means that if less than 512 bits have

been transmitted onto the network, the transmission will

be terminated immediately, generating a runt packet. If

512 bits or more have been transmitted, the message

will have the current FCS inverted and appended at the

next byte boundary to guarantee an FCS error is de-

tected at the receiving station.

APERREN does not affect the reporting of address par-

ity errors or data parity errors that occur when the

PCnet-PCI II controller is the target of the transfer.

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