AM79C970AVCW datasheet(44/219 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C970A

The following figure shows two non-burst read transac-

tions. The first transaction has zero wait states. In the

second transaction, the target extends the cycle by as-

serting

TRDY one clock later.

19436A-16

FRAME

CLK

IRDY

TRDY

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0110

PAR

2345678

DATA

ADDR

DATA

PAR

0000

0110

0000

Figure 13. Non-Burst Read Transfer

Basic Burst Read Transfer

The PCnet-PCI II controller supports burst mode for all

bus master read operations. The burst mode must be

enabled by setting BREADE (BCR18, bit 6). To allow

burst transfers in descriptor read operations, the

PCnet-PCI II controller must also be programmed to use

SWSTYLE THREE (BCR20, bits 7–0). All burst read

accesses to the initialization block and descriptor ring

are of the PCI command type Memory Read (type 6).

Burst read accesses to the transmit buffer typically are

longer than two data phases. When MEMCMD (BCR18,

bit 9) is cleared to ZERO, all burst read accesses to the

transmit buffer are of the PCI command type Memory

Read Line (type 14). When MEMCMD (BCR18, bit 9) is

set to ONE, all burst read accesses to the transmit buffer

are of the PCI command type Memory Read Multiple

(type 12). AD[1:0] will both be ZERO during the address

phase indicating a linear burst order. Note that during a

burst read operation, all byte lanes will always be active.

The PCnet-PCI II controller will internally discard

unneeded bytes.

The PCnet-PCI II controller will always perform only a

single burst read transaction per bus mastership period,

where transaction is defined as one address phase and

one or multiple data phases. The PCnet-PCI II controller

supports zero wait state read cycles. It asserts

IRDY im-

mediately after the address phase and at the same time

starts sampling

DEVSEL. FRAME is deasserted when

the next to last data phase is completed.

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