45111 datasheet(99/184 Pages) ETC2

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10 SX Special Features and Coding Tips

SX-Key/Blitz Development System Manual 2.0

• Parallax, Inc. • Page 99

10.4 All About Interrupts

The SX20/28 chip allows for up to nine sources of interrupts; eight external and one internal. The

SX48/52 chip allows for up to 17 sources of interrupts; 10 external and one internal. Any or all of the

port B I/O pins can be configured as external interrupts. See Chapter 10.2.6 – Wakeup (Interrupt) on

Edge Detection

for information on configuring external interrupts. The internal interrupt can be

configured to occur upon a rollover condition within the Real Time Clock Counter (RTCC) register. A

special return-from-interrupt command may also be used to adjust the value of the RTCC to cause

interrupts to occur at a specific time interval. See section 10.4.1 for more information.

In addition to the interrupts supported by the SX20/28, with the SX48/52 devices, six different internal

interrupts can be configured for the Timer 1 and Timer 2 overflow and R1/R2 counter comparison reg-

isters.

These interrupt options can be very powerful features but can also cause havoc if not configured or

understood properly. If using interrupts of any kind is desired, the following items should be reviewed.

•

Interrupt Vector:

The interrupt vector in the SX chip points to address $0 and is not configurable. The

interrupt routine must reside at location $0 to be properly executed upon an interrupt event.

•

Auto Interrupt Disable:

As soon as an interrupt occurs, additional interrupts are automatically

ignored by the SX chip until the interrupt routine is completed. This prevents the interrupt routine

from being interrupted and prevents the loss of return vector data. This is also one of the most

important considerations when working with interrupts; you can not immediately (without jitter)

process more than one interrupt at a time.

Note: Should additional interrupts occur, the SX chip does not automatically queue up interrupts for future

processing. See Interrupt Queuing, below, for more information.

•

Latency Delays:

When an interrupt occurs, there is a latency delay before the interrupt routine is

actually activated. For the internal RTCC rollover, this latency is exactly 3 clock cycles in Turbo

mode and 8 clock cycles in Compatible mode. For the external interrupts, the latency delay is

exactly 5 clock cycles in Turbo mode and 10 clock cycles in Compatible mode. Latency may vary by

as much as +1 instruction cycle when interrupting on external asynchronous events, thus a high

clock speed may be necessary to lessen the effects.

•

Interrupt Routine Size:

Normally it is a requirement for an application to process every interrupt

without missing any. To ensure this happens, the longest path through the interrupt routine must

take less time than the shortest possible delay between interrupts.

•

Interrupt Queuing:

If an external interrupt occurs during the interrupt routine, the pending register

will be updated but the trigger will be ignored unless interrupts had first been turned off at the

beginning of the routine and turned on again at the end. This also requires that the new interrupt

doesn’t occur before interrupts are turned off in the interrupt routine. If there is a possibility of

extra interrupts occurring before they can be disabled, the SX will miss those interrupt triggers.

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