RM0319 datasheet(77/368 Pages) STMICROELECTRONICS

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RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

77/368

Table 29 shows the system behavior with port pairing. Since ports P4 - P5 are still at a lower

priority, they will be ignored unless none of the higher priority ports (i.e. P0, P1, P2 or P3)

are requesting. Note the following points:

●

When either port of a port pair wins arbitration, the counters for both ports of the pair

increment.

●

In Cycle 3, the port pair P0/P1 reaches its allocated relative priority.

Note:

The port pair dynamically moves to the bottom of the scan order.

●

In Cycle 8, the port pair P4/P5 reaches its allocated relative priority. However, since

these are the only requests at priority 1, the scan order does not change.

Table 28.

System G specifications

Parameter

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

ahbX_priority0_relative_priority

ahbX_priority1_relative_priority

ahbX_port_ordering

weighted_round_robin_weight_sharing

1 (Paired)

0 (Not Paired)

1 (Paired)

Table 29.

System G operation

Cycle

Ports Requesting

Arbitration

Winner

Next Counter

Next Scan Order

P0 P1 P2 P3 P4 P5

Priority 0: P0-P1-P2-P3

Priority 1: P4-P5

P0-P1-P2-P3

P5-P4

P0-P1-P2-P3

P5-P4

P0-P1-P2-P3

P5-P4

P2-P3-P0-P1

P5-P4

P2-P3-P0-P1

P5-P4

P2-P0-P1-P3

P5-P4

P2-P0-P1-P3

P5-P4

P2-P0-P1-P3

P5-P4

P2-P0-P1-P3

P5-P4

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