RM0319 datasheet(83/368 Pages) STMICROELECTRONICS

83 / 368 page

RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

83/368

Before the memory devices are removed from self-refresh, the MPMC and memory

clocks will be gated on.

6.4.2

Low power mode control

The memory controller may enter and exit the various low power modes in the following

ways:

●

Automatic Entry: When the memory controller is idle, 4 different timing counters begin

counting the cycles of inactivity. If any of the counters expires, the memory controller

enters the low power mode associated with that counter.

●

Manual Entry: The user may set any low power mode by setting the bit of the

lowpower_control parameter associated with the desired mode. The memory controller

will enter the selected low power mode when it is has completed its current burst.

Automatic and Manual entry methods are both controlled by two parameters:

lowpower_control and lowpower_auto_enable. The lowpower_control parameter contains

individual enable/disable bits for each low power mode, and the lowpower_auto_enable

parameter controls whether each mode will be entered automatically or manually.

Automatic entry

Automatic Entry will occur as all the following conditions are matched:

●

The mode is programmed for automatic entry by setting the relevant bit in the

lowpower_auto_enable parameter to 1'b1.

●

The particular mode is enabled in the lowpower_control parameter.

●

The memory controller is idle.

●

The counter associated with this mode expires.

There are 4 counters to full cover the 5 low power modes. There are separate counters for

each of the three memory self-refresh low power modes (Modes 3, 4 and 5). Memory

Power-Down mode (Mode 1) and Memory Power-Down with Memory Clock Gating mode

(Mode 2) share the same counter.

The counters determine the number of idle cycles before entering into the associated low

power mode. Every counter is re-initialized each time there is a new READ or WRITE

transaction entering or executing in the memory controller. This guarantees that the MPMC

will not enter any of the low power modes when active.

Each low power mode can be entered through automatic entry, and will be exited

automatically whenever any of the following conditions occur:

●

A new READ or WRITE transaction appears at the MPMC interface.

●

The MPMC must refresh the memory when in either of the power-down modes (Modes

1 or 2). After completing the memory refresh, the MPMC re-enters power-down.

●

The counter for a deeper low power mode expires. The MPMC must exit the current low

power mode in order to enter the deeper low power mode. A minimum of 15 cycles

occur between exit from one low power mode before entering into the next low power

mode, even if the counters expire within 15 cycles of each other.

Note:

The memory controller will not enter a less deep low power mode, regardless of which

counter expires.

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