RM0319 datasheet(99/368 Pages) STMICROELECTRONICS

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RM0319

Serial NOR Flash controller (SMI)

Doc ID 022640 Rev 3

99/368

Read while write mode

If a read request occurs for the bank which is in programming phase, the AHB bus is stalled

until no write in progress (WIP = 1‘b0). (please refer to SMI_SR register description for

details on WIP bit).

If a read request occurs for another bank, the read status register sequence is stopped, then

the read request is served and, finally, the read status register sequence is sent again to the

memory bank being programmed.

It follows that during a read while write, the selected external SPI memory is released after

the read command, in order to send the read status register sequence.

Erase and write status register

In case of serial Flash, an erase may be necessary before writing. Due to incompatibility

between different serial Flash vendors, erase and write status register can be done only in

software mode.

It is mandatory to send previously the write enable instruction through Software mode only

(that is, setting the WEN bit in SMI_CR2 register, in order to avoid corruption of the WM bit

in the SMI_SR register. Indeed, the end of either internal Flash erase or write status register

cannot be checked by hardware mode, preventing generation of write complete interrupt. On

the other hand, WIP bit can be checked by continuously sending a read status register

command.

7.4

Clocks

The memory clock (SMI_CLK) is generated by SMI through its programmable prescaler unit

(Section 7.3.1), as depicted in Figure 21.

The incoming AHB bus frequency fAHB (HCLK signal) is divided by the value stored in the

PRESC field of SMI_CR1 register, resulting in the SMI clock frequency fSMI_CLK:

●

fSMI_CLK = fAHB / 2*(PRESC value)

that is,

●

tSMI_CLK = tAHB · 2*(PRESC value)

being tSMI_CLK and tAHB the clock period of the SMI clock and the AHB bus, respectively.

Note:

If PRESC is an even value, high time and low time of SMI clock are both equal to half a

tSMI_CLK. In contrast, in case PRESC is an odd value:

tSMI_CLK, high= [(PRESC - 1) / 2]

tSMI_CLK, low = [(PRESC + 1) / 2]

7.4.1

Latencies

Assuming that SMI is not busy by now, the nominal latency for a 32 bit single read to a non-

incrementing serial Flash address, is:

●

73 tAHB maximum, if PRESC = 1 (that is, tAHB = tSMI_CLK).

●

(68 tSMI_CLK + 5 tAHB) maximum, if PRESC > 1 (that is, tAHB ≠ tSMI_CLK, and specifically

tSMI_CLK > tAHB),

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