LM4560 datasheet(26/54 Pages) NSC

26 / 54 page

3.0 Register Description (Continued)

Bit 2 (SB_IRQ) is sound blaster IRQ bit. Active high.

Bit[2] = sbirq (signal from Legacy Audio block)

Bit 3 (MPU401_IRQ) is MPU401 IRQ bit. Active high.

Bit[3] = mpu401irq (signal from Legacy Audio block)

Bit 4 (OPL3_IRQ) is OPL3 timer IRQ bit. Active high.

Bit[4] = timerirq & opltimer_ie

Bit 5 (ADDRESS_IRQ) is Wave-table Address Engine IRQ

bit. Active high.

Bit[5]=(| AINT_A[31:0])|(| AINT_B[31:0] )

Bit 6 (ENVELOPE_IRQ) is Wave-table Envelope Engine IRQ

bit. Active high.

Bit[6] = | EINT[31:0]

Bit 7 (ST_IRQ) is Sample Timer IRQ bit. Active high.

Bit[7] = ST_IRQ_En | ST_TARGET_REACHED

Bit [9:8] (read/write) are current status bits of wave-table &

legacy audio engine.

Bit 8 (PB_UNDERUN) is playback FIFO underrun status bit.

Active high.

This bit will be set to ‘1’ if playback is running & FIFO is

empty & f48 clock is coming.

Bit 9 (REC_OVERUN) is recording overrun status bit. Active

high.

This bit will be set to ’1’ if recording is running & rec_req_ is

active & data_rdy haven’t come.

Bit 10 (mixer_underflow_flag) is a flag which indicates the re-

sult of mixer accumulator is less than 80000h.

This bit will be set to ‘1’ once accumulator underflows.

Write ‘1’ will clear this bit.

Bit 11 (mixer_overflow_flag) is a flag which indicates the re-

sult of mixer accumulator exceeds 7FFFFh.

This bit will be set to ‘1’ once accumulator overflows.

Write ‘1’ will clear this bit.

Bit 15 (ST_TARGET_REACHED) is a flag with ‘1’ indicates

STIMER counter has been equal to ST_TARGET.

This bit will be set to ‘1’ once STIMER counter is equal to

ST_TARGET.

Write ‘1’ will clear this bit.

Bit 16 (PB_24K_MODE) is playback 48k/24k mode control

bit.

0: (default) Wave engine drives sample to CODEC at 48 kHz

1: Wave engine drives sample to CODEC at 24 kHz (in this

mode, Delta should be programmed twice as that in 48Khz

mode).

Bit 17 (opltimer_ie) is OPL3 timer interrupt enable bit.

0: disable

1: enable

Bit 23 (ST_IRQ_En) is ST IRQ enable bit.

0: disable

1: enable

Bit 24 (ACGPIO_IRQ) is AC97 GPIO interrupt request.

ACGPIO_IRQ = Reg4Ch[1] & Reg4Ch[3] | Reg4Ch[2] &

Reg4Ch[4].

All other bits are reserved bits.

3.4.9.14 STAR_B (START Command and Status

Address: AudioBase + B4h

Size:

32 bits

Type:

Read/Write

Default:

0000h

This register and STOP_B are used as Bank B channel start/

stop command register when they are written, and used as

Bank B channel running/stopped status register when they

are read. Bit n is for channel n.

Reading from this I/O port will return the running/stopped

status of Bank B 32 voice channels.

0: Stopped.

When bit n is read as ‘0’, it means any operation of channel

n, including address generation, sample data fetching, inter-

polation, and envelope calculation is stopped. And this chan-

nel has no contribution to the digital mixer. This bit will be re-

set from ‘1’ to ‘0’ in four cases.

(1) when a ‘1’ is written to the corresponding bit in register

STOP_B.

(2) when out of data, i.e. when sample loop disabled and

CSO (Current Sample Offset)

≥ ESO (End Sample Offset).

when Ec (current envelope) drops down to −63.984375 dB.

when current envelope buffer is in delay-stop mode, and

EDLY count down to ‘0’.

1: Running.

When bit n is read as ‘1’, it means channel n is working. This

bit will be set from ‘0’ to ‘1’ only when a ‘1’ is written to the

corresponding bit in register START_B.

Writing to this I/O port means issuing a start command to ad-

dress engine and envelope engine in expected channel.

0: Ignore.

A ‘0’ written to bit n will not change the status of channel n.

1: Start.

A ‘1’ written to bit n will start channel n’s address engine and

envelope engine and also set the status bit n to ‘1’.

3.4.9.15 STOP_B (Channel STOP Command and Status

Address: AudioBase + B8h

Size:

32 bits

Type:

Read/Write

Default:

0000h

Reading from this I/O port will return the same value as from

the last register START_B.

Writing to this I/O port means issuing a stop command to ad-

dress engine and envelope engine in expected channel.

0: Ignore.

A ‘0’ written to bit n will not change the status of channel n.

1: Stop.

A ‘1’ written to bit n will stop channel n’s address engine and

envelope engine, and also reset the corresponding status bit

to ‘0’.

3.4.9.16 CSPF_B (Bank B Current Sample Position

Flag)

Address: AudioBase + BCh

Size:

32 bits

Type:

Read/Write

Default:

00000000h

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