LM4560 datasheet(27/54 Pages) NSC

27 / 54 page

3.0 Register Description (Continued)

This register will show a flag which indicates the Bank B’s

current sample is in a range between ESO/2 to ESO or in a

range before ESO/2 (ESO is offset from loop begin to loop

end). And this flag will be used for sample data double buff-

ering control. Bit n is for channel n.

0: Before ESO/2

1: From ESO/2 to ESO

When channel n is stopped, bit n will be reset to ‘0’.

3.4.9.17 SBBL & SBCL (Sound Blaster Base Block

Length & Current Block Length)

Address: AudioBase + C0h

Size:

32 bits

Type:

Read/Write

Default:

00000000h

SBBL(Bit 31–16) is sound blaster base block length

SBCL(Bit 15–0) is current value of sound blaster block

length counter

If sound blaster DMA loop is enabled (SBCTRL[3]=1), every

time when SBCL changed from 0 to FFFFh, a INT will be is-

sued, the contents of SBCL is reloaded from SBBL, and

DMA operation continues.

If sound blaster DMA loop is not enabled (SBCTRL[3]=0),

every time when SBCL changed from 0 to FFFFh, a INT will

be issued, the contents of SBCL is reloaded from SBBL, and

set LegacyCMD to 101(pause).

SBCTRL bit 7 is used to determine the counter operation

mode (byte count or word count). The counter is a count

down counter.

3.4.9.18 SBCTRL & SBE2R & SBDD (Sound Blaster

Control)

Address:

AudioBase + C4h

Size:

32 bits

Type:

Read/Write

Default:

00000000h

Description SBE2R (Sound Blaster DMA Testing Byte Data

SBDD (Sound Blaster Direct Playback Date

SBCTRL (Sound Blaster Control)

SBE2R(Bit 31–24) is sound blaster DMA testing byte com-

mand data port (write only)

Any time after Bit 31–24 has ever been written, E2Status

(source from wave engine) will be set high. E2Status will be

cleared after the testing byte has been sent to the system lo-

cation.

SBDD(Bit 15–8) is sound blaster direct mode playback data

port

SBCTRL(Bit 7–0) is legacy sound blaster voice in/out control

Bit 7

0 8 bit data format

1 16 bit data format

Bit 6

0 mono

1 stereo

Bit 5

0 unsigned data format

1 signed data format

Bit 4

0 playback

1 recording

Bit 3 sound blaster DMA loop enable control

0 loop disabled.

1 loop enabled.

Bit 2..0 LegacyCMD

000 stop: No any operation. No contribution to Digital Mixer

001 run: Normal operation.

010 silent_DMA : SBCL will count; CA, CBC won’t count. No

data fetching. No interpolation. No contribution to Digital

Mixer

011 reserve

100 silent_SB : SBCL, CA & CBC will count as the same as

run mode. No data fetching. No interpolation. No contribution

to Digital Mixer

101 pause: SBCL, CA & CBC don’t change.

let SBALPHA unchanged, CACHE_HIT=1 drive current LD

(or LD_L, LD_R) to Digital Mixer

110 reserve

111 Direct_playback: SBCL, CA & CBC don’t change.

drive SBDD to Digital Mixer

All other bits are reserved bits.

3.4.9.19 STimer (Playback Sample Timer)

Address: AudioBase + C8h

Size:

32 bits

Type:

Read/Write

Default:

00000000h

Bit 31–0 (STimer) will show current state of the sample timer

counter which will count up every f48k clock and will be reset

when RST_Stimer bit being written. Active high.

3.4.9.20 LFO_B And I2S_DELTA (Bank B Low

Frequency Oscillator Control)

Address: AudioBase + CCh

Size:

32 bits

Type:

Read/Write

Default:

00000000h

Bit 31–27 Reserved–Read Only 00000b

Bit 26–16 is used for Bank B LFO control.

Bit 26 (LFO_E_B) is Bank B LFO enable bit.

0: disabled

1: enabled

Bits 25–24 (LFO_R_B) is clock rate select of Bank B LFO

counter.

00: LFO counter clock rate is 48 kHz

01: LFO counter clock rate is 48 kHz/4

10: LFO counter clock rate is 48 kHz/16

11: LFO counter clock rate is 48 kHz/64

Bits 23–16 (LFO_INIT_B)is the initial value of the Bank B

LFO counter which will count down to 0 then reload.

Bit 15–13 reserved.

Bit 12–0 (I2S_DELTA) (Read only) This register returns the

auto-detected DELTA of I2S input (f

i2s/f48k).

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