LM4560 datasheet(50/54 Pages) NSC

50 / 54 page

4.0 Functional Description (Continued)

Default: FFh

Bit 7..0 Low Byte of SB DMA Current Block Length Re-

mained - 1

4.2.1.22.2.4 SBDMAC SB DMA Current Block Length High

Byte

SB ESP Address: 1h

Size: 8 bits

Type: Write Only For SB ESP

Read Only For Wave Engine

Default: 07h

Bit 7..0 High Byte of SB DMA Current Block Length Re-

mained - 1

4.2.1.22.2.5 SBDMAL SB DMA Base Block Length Low Byte

SB ESP Address: 2h

Size: 8 bits

Type: Write Only For SB ESP

Read Only For Wave Engine

Default: FFh

Bit 7..0 Low Byte of SB DMA Base Block Length - 1

4.2.1.22.2.6 SBDMAL SB DMA Base Block Length High Byte

SB ESP Address: 3h

Size: 8 bits

Type: Write Only For SB ESP

Read Only For Wave Engine

Default: 07h

Bit 7..0 High Byte of SB DMA Base Block Length - 1

SBDMAL, SBDMAC are byte count when SBCTRL Bit 7 is 0.

SBDMAL, SBDMAC are word count when SBCTRL Bit 7 is

When SBDMAC changed from 0 to FFFFh, a SBBLOVER in-

terrupt signal should be generated and sent to SB ESP en-

gine. Also the SBDMAC is reload from SBDMAL.

4.2.1.22.2.7 SBCTRL SB DMA Running Mode and Data For-

mat Register

SB ESP Address: 4h

Size: 8 bits

Type: Write Only For SB ESP

Read Only For Wave Engine

Default: 00h

Bit 7

0: 8 bit data format

1: 16 bit data format

Bit 6

0: mono

1: stereo

Bit 5

0: unsigned data format

1: signed data format

Bit 4

0: playback

1: recording

Bit 3

0: stop running after current block length expired

1: continue running after current block length expired

Bit 2..0 X legacy channel working mode

000 stop

001 run

010 silent audio

011 reserved

100 silent DMA

101 pause

110 reserved

111 direct mode play

4.3 SERIAL INTERFACE

4.3.1 AC-97 Interface

4.3.2 I2S Interface

4.3.3 S/PDIF

4.4 POWER MANAGEMENT

Term:

Header standard PCI configuration space standard header

type 0

HIFW

host interface write

HRST

H/W Reset on PCI bus

SRST

S/W Reset

Audio Device Run: DC97, AC97 and PCI INTF at

full power on state

Audio Device Pause: DC97 clock off

Audio Device Close: DC97 clock off, Inactivity

Timer running, AC97 clock is about to be turned off

D3hot

Audio Device Clock Off: DC97 clock off, AC97 clock

off, PCI clock keep running

D3cold Audio Device Power Off: V

CC is taken off.

4.4.1 Power Management for D0–D3 State

When at D0 state, DC97, AC97 and PCI INTF are running

normally. After power on reset, audio device is at D0 state.

Once enter D1 state, if DC_PM_EN_ (PM_CFG bit[1]) = 0,

clock of DC97 will be shut off and kept staying low after au-

dio engine enters Pause or Stop state, i.e., Audio_clk will be

shut off when Audio_idle flag is set.

Once enter D2 state, DC97 clock will be turned off as the

same way as in D1 state. And also, the Inactivity Timer be-

gins to count immediately.

When the counter expired (around 30 seconds later after en-

ter D2 state), if Timer_PME_EN (PM_CFG bit[7]) = 1, a PME

will be issued; otherwise, no PME issued but PM_ST will be

set to 11b (D3) by chip.

Once enter D3 state, if AC_PM_EN_ (PM_CFG bit) = 0, the

bit clock of AC97 will be shut off after a H/W power down

command sequence through AC-link generated by DC97.

A one shot signal called ac97pm_pulse (generated by PM

logic) is used to inform DC97 to generate those power down

sequences.

4.4.2 D0–D3 State Transition Table

Present

State

State Change Way

D3cold

HRST

D3hot

SRST

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