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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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LM4560 Arkusz danych(PDF) 10 Page - National Semiconductor (TI) |
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LM4560 Arkusz danych(HTML) 10 Page - National Semiconductor (TI) |
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10 / 54 page  3.0 Register Description (Continued) 0: (Default) Normal (PME is controlled by bit[8] PME_En) 1: PME can be asserted independent of bit[8] (PME_En). Writing 0 to this bit has no effect. Writing 1 to this bit will clear this bit, and also cause chip to stop asserting PME. Bit 14–13 (Data_Scale) Read only as 00b. Bit 12–9 (Data_Select) Read only as 0000b. Bit 8 (PME_En) Read/Write. 0: (Default) PME is disabled to be asserted. 1: PME is enabled to be asserted. Bit 7–2 Reserved. Read only as 000000b. Bit 1–0 (PM_ST) Power State. Read/Write. Read will return current Power State, write will set to new state. 00 D0 01 D1 10 D2 11 D3 hot 3.2 AUDIO PROCESSOR REGISTER MAP: IO Offset +3h +2h +1h +0h 00h DMAR3 DMAR2 DMAR1 DMAR0 04h DMAR7 DMAR6 DMAR5 DMAR4 08h DMAR11 DMAR10 DMAR9 DMAR8 0Ch DMAR15 DMAR14 DMAR13 DMAR12 10h SBR3/SBR1 SBR2 SBR1/SBR3 SBR0 14h RSVD SBR6 SBR5 SBR4 18h RSVD SBR7 RSVD RSVD 1Ch SBR10 SBR9 RSVD SBR8 20h MPUR3 MPUR2 MPUR1 MPUR0 24h–2Ch RSVD 30h RSVD RSVD GAMER1 GAMER0 34h GAMER2 38h GAMER3 3Ch RSVD 40h ACWR 44h ACRD 48h SCTRL 4Ch ACGPIO 50h ASR0 54h RSVD ASR2 RSVD ASR1 58h ASR3 5Ch ASR6 ASR5 RSVD ASR4 60h AOPLSR0 70h SPDIF_CS 74h RSVD 78h SubSystem ID SubVendor ID 7Ch PCI ID read GPcontrol GPO GPI 80h START_A 84h STOP_A 88h DLY 8Ch SIGN_CSO 90h CSPF_A 94h CEBC 98h AIN_A 9Ch EINT A0h GC CIR A4h AINTEN_A A8h MUSICVOL WAVEVOL ACh SBDELTA/SBDELTA_R RSVD www.national.com 10 |
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