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MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

Features

2Features

This section summarizes features of the MPC755 implementation of the PowerPC architecture. Major features of

the MPC755 are as follows:

•

Branch processing unit

— Four instructions fetched per clock

— One branch processed per cycle (plus resolving two speculations)

— Up to one speculative stream in execution, one additional speculative stream in fetch

— 512-entry branch history table (BHT) for dynamic prediction

— 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay

slots

•

Dispatch unit

— Full hardware detection of dependencies (resolved in the execution units)

— Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1,

fixed-point unit 2, floating-point)

— Serialization control (predispatch, postdispatch, execution serialization)

•Decode

— Register file access

— Forwarding control

— Partial instruction decode

•

Completion

— Six-entry completion buffer

— Instruction tracking and peak completion of two instructions per cycle

— Completion of instructions in program order while supporting out-of-order instruction execution,

completion serialization, and all instruction flow changes

•

Fixed point units (FXUs) that share 32 GPRs for integer operands

— Fixed Point Unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical

— Fixed Point Unit 2 (FXU2)—shift, rotate, arithmetic, logical

— Single-cycle arithmetic, shifts, rotates, logical

— Multiply and divide support (multi-cycle)

— Early out multiply

•

Floating-point unit and a 32-entry FPR file

— Support for IEEE standard 754 single- and double-precision floating-point arithmetic

— Hardware support for divide

— Hardware support for denormalized numbers

— Single-entry reservation station

— Supports non-IEEE mode for time-critical operations

— Three-cycle latency, one-cycle throughput, single-precision multiply-add

— Three-cycle latency, one-cycle throughput, double-precision add

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