MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

13

Electrical and Thermal Characteristics

4.2

AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC755. After fabrication, functional parts are sorted

by maximum processor core frequency as shown in Section 4.2.1, “Clock AC Specifications,” and tested for

conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus

(SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core

frequency; see Section 10, “Ordering Information.”

4.2.1

Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 3.

Table 8. Clock AC Timing Specifications

At recommended operating conditions (see Table 3)

Characteristic

Symbol

Maximum Processor Core Frequency

Unit

Notes

300 MHz

350 MHz

400 MHz

MinMax

MinMax

MinMax

Processor frequency

200

300

200

350

200

400

MHz

1

VCO frequency

400

600

400

700

400

800

MHz

1

SYSCLK frequency

25

100

25

100

25

100

MHz

1

SYSCLK cycle time

10

40

10

40

10

40

ns

SYSCLK rise and fall time

—2.0

—2.0

—2.0

ns

2

—1.4

—1.4

—1.4

ns

2

SYSCLK duty cycle measured at

40

60

40

60

40

60

%

3

SYSCLK jitter

—

±150

—

±150

—

±150

ps

3, 4

Internal PLL relock time

—

100

—

100

—

100

µs3, 5

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core)

frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3]

2. Rise and fall times measurements are now specified in terms of slew rates, rather than time to account for selectable I/O bus interface levels.

3. Timing is guaranteed by design and characterization.

4. This represents total input jitter—short term and long term combined—and is guaranteed by design.

5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a

and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the

PLL-relock time during the power-on reset sequence.