MPC755 datasheet(5/56 Pages) MOTOROLA

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

Features

— Four-cycle latency, two-cycle throughput, double-precision multiply-add

•

System unit

— Executes CR logical instructions and miscellaneous system instructions

— Special register transfer instructions

•

Load/store unit

— One-cycle load or store cache access (byte, half-word, word, double word)

— Effective address generation

— Hits under misses (one outstanding miss)

— Single-cycle unaligned access within double-word boundary

— Alignment, zero padding, sign extend for integer register file

— Floating-point internal format conversion (alignment, normalization)

— Sequencing for load/store multiples and string operations

— Store gathering

— Cache and TLB instructions

— Big- and little-endian byte addressing supported

•

Level 1 cache structure

— 32K, 32-byte line, eight-way set-associative instruction cache (iL1)

— 32K, 32-byte line, eight-way set-associative data cache (dL1)

— Cache locking for both instruction and data caches, selectable by group of ways

— Single-cycle cache access

— Pseudo least-recently-used (PLRU) replacement

— Copy-back or write-through data cache (on a page per page basis)

— MEI data cache coherency maintained in hardware

— Nonblocking instruction and data cache (one outstanding miss under hits)

— No snooping of instruction cache

•

Level 2 (L2) cache interface (not implemented on MPC745)

— Internal L2 cache controller and tags; external data SRAMs

— 256K, 512K, and 1 Mbyte two-way set-associative L2 cache support

— Copy-back or write-through data cache (on a page basis, or for all L2)

— Instruction-only mode and data-only mode

— 64-byte (256K/512K) or 128-byte (1M) sectored line size

— Supports flow through (register-buffer) synchronous BurstRAMs, pipelined (register-register)

synchronous BurstRAMs (3-1-1-1 or strobeless 4-1-1-1) and pipelined (register-register) late write

synchronous BurstRAMs

— L2 configurable to cache, private memory, or split cache/private memory

— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported

— 64-bit data bus

— Selectable interface voltages of 2.5 and 3.3 V

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