UPD360 datasheet(27/221 Pages) MICROCHIP

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DS00002084C-page 27

UPD360

The instructions supported by the SPI slave controller are listed in Table 6-1. Unsupported instructions are reserved and

must not be used.

6.2.1

DEVICE INITIALIZATION

Until the device has been initialized to the point where the various configuration inputs are valid, the SPI interface will

not respond to or be affected by any external pin activity.

Once device initialization completes, the SPI interface will ignore the pins until a rising edge of SPI_CS is detected.

If the device initialization completes during an active cycle (SPI_CS low), the trailing end of the frame must be seen

(SPI_CS returning high) before any internal registers are affected or the state of the SPI interface changes.

The first SPI access after device initialization must always be a dummy read to the SPI Test Register (SPI_TEST)

(UPD360-C Only).

6.2.1.1

SPI Slave Read Polling for Initialization Complete

With an external weak pull-up resistor present on SPI_DO, a value of FFh will appear to have been read from any inter-

nal register while the device is uninitialized. By verifying the SPI Test Register (SPI_TEST) (UPD360-C Only) has at

least one “0” bit in it, it is possible to tell when the device is initialized.

6.2.2

ACCESS DURING AND FOLLOWING POWER MANAGEMENT

The Wake event on SPI traffic is local to the specific device, and does not affect the states of other devices even on the

same SPI bus. Until waking is complete, the SPI interface holds the SPI_DO pin low for the duration of the SPI_CS low

time.

Until the device is awake, then, any Read access performed by the Master will appear to have returned all “1” bits. To

determine when the device is awake and the SPI interface functional, the SPI Test Register (SPI_TEST) (UPD360-C

Only) should be repeatedly polled by the Master in separate frames (SPI_CS low then high). Once a correct, non-zero

value is read, the interface can be considered functional. As an alternative to polling, an IRQ_N pin assertion can be

used to indicate the device is ready.

Once the power management mode changes back to ACTIVE, the SPI interface will still ignore the SPI_CLK and

SPI_DI pins, following SPI_CS low with SPI_DO low, until SPI_CS is seen high. At the next SPI_CS falling edge, SPI

communication will continue normally.

At any time after performing SPI traffic, the device will not go back to a non-communicating power state until explicitly

allowed to do so by a command from the SPI Master.

TABLE 6-1:

SPI INSTRUCTIONS

Instruction

Description

Bus Bit

Width

Inst. Code

Address

Bytes

Dummy

Bytes

Data bytes Max Freq.

Read

FASTREAD

Read, higher

speed format

10Bh

1 to



25 MHz

Write

WRITE

Write

02h

1 to



25 MHz

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