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UPD360 Arkusz danych(PDF) 29 Page - Microchip Technology

Numer części UPD360
Szczegółowy opis  Highly Integrated Small Form Factor USB Type-C??Power Delivery 2.0 Port Controller
PDF  221 Pages
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Producent  MICROCHIP [Microchip Technology]
Strona internetowa  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

UPD360 Arkusz danych(HTML) 29 Page - Microchip Technology

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 2016-2017 Microchip Technology Inc.
DS00002084C-page 29
UPD360
6.2.3.2
Fast Read
Figure 6-2 illustrates a typical single and multiple register fast read for SPI mode.
6.2.4
SPI WRITE COMMANDS
The following write commands are supported by the SPI slave controller:
• Write
• Multiple Writes
6.2.4.1
Write
The Write instruction provides the instruction code and address and data bytes on the SPI_DI pin, one bit per clock.
The SPI transfer is started by the Master first driving SPI_CS active. The 8-bit WRITE instruction, 02h, is given on the
SPI_DI pin, followed by the two address bytes. The address bytes specify a byte address within the device, and a Direc-
tion control subfield (DIR).
The data immediately follows the address bytes on the SPI_DI pin, starting with the most significant bit of the first byte.
The data is input from the SPI_DI pin by the device, shifted in on each subsequent rising clock edge.
6.2.4.2
Multiple Writes
Multiple writes are performed by the Master by continuing the clock pulses and SPI_DI data while SPI_CS remains
active. The upper two bits [15:14] of the address constitute the DIR subfield, and specify auto-incrementing (DIR=00b)
or auto-decrementing (DIR=10b) or Static addressing. The internal Byte address is incremented, decremented, or kept
fixed (Static) based on these bits. Maintaining a fixed internal address may be useful for FIFO access, register “bit-bang-
ing” or other repeated activity.
The data write to the register occurs after the full register contents are input: this depends on the defined size of the
register. In the event that the full register is not written when SPI_CS is returned high, the write is considered invalid and
the register is not affected.
The SPI_CS input is then brought inactive to conclude the cycle.
FIGURE 6-2:
SPI FAST READ
SPI Fast Read Single Register
SPI_CLK (Mode 0)
SPI_DI
00
00
1
X
Instruction
1
Address
SPI_DO
Data
A
1
3
X
SPI Fast Read Multiple Registers
10
D
7
D
6
D
5
Z
Z
X
SPI_CLK (Mode 3)
SPI_CS
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
3
3
3
4
3
5
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
3
3
3
4
3
5
3
7
3
8
3
9
4
0
X
X
3
7
3
8
3
9
4
0
D
2
D
0
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
SPI_CLK (Mode 0)
SPI_DI X
Instruction
Address
X
SPI_DO
A
1
3
...
X
...
Z
SPI_CLK (Mode 3)
SPI_CS
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
X
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
...
D
7
D
6
D
5
D
2
D
0
...
D
7
D
6
D
5
Z
X
X
...
...
x
x
x
x
x
x
x
x
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
Dummy
x
x
x
x
x
x
x
x
Dummy
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
2
3
3
3
4
3
5
3
3
3
4
3
5
00
00
1
1
10
D
1
D
1
Data 1...
Data m
Data m+1...Data n
...
Inc / Dec /
Static
DIR
Inc / Dec /
Static
DIR
D
4
D
3
3
6
3
6
D
2
D
0
D
1
(Irrelevant to 1-byte Reads)



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