UPD360 datasheet(33/221 Pages) MICROCHIP

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DS00002084C-page 33

UPD360

7.5

Power Delivery MAC Wakeup

The PD MAC is capable of asynchronous wakeup upon reception of a PD packet. This enables the device to be placed

in STANDBY mode and minimize power consumption.

The following steps illustrate the RX PD MAC wake function. Initially the Ring Oscillator and the 48 MHz Relaxation

Oscillator are disabled. The 20 KHz Keep Alive Oscillator is enabled, but not used in the wake process.

In order to receive a PD message, the RX AFE is enabled via software and the trip point is set via the CC RX

DAC Control Register (CC_RX_DAC_CTL) and CC RX DAC Filter Register (CC_RX_DAC_FILT).

The PD MAC is configured and enabled via software.

The device is powered down. Software disables the 48 MHz Relaxation Oscillator, and Ring Oscillator if enabled,

via the Clock Control Register (CLK_CTL).

After some time elapses, the device receives a PD message from the attached partner.

The PD MAC asynchronously detects preamble activity on the CC line and enables the 48 MHz Relaxation Oscil-

lator.

The oscillator is operational in approximately 5 us, at which point the PD MAC is operational.

The PD MAC receives the remainder of the preamble and stores the message into the RX FIFO, and in accor-

dance with the PD protocol, responds with GoodCRC as required.

An interrupt is issued via assertion of the IRQ_N pin.

Software services the interrupt via I2C, reads the PD message, and responds as required.

10. The device is then powered down. Software disables the 48 MHz Relaxation Oscillator and Ring Oscillator via

the Clock Control Register (CLK_CTL).

11. The device remains powered down until the next PD message is received.

7.6

Interrupt Assertion from STANDBY

When the device is in STANDBY it is able to detect a number of events that may be configured to assert the IRQ_N pin

upon being appropriately programmed via software. The logic detecting such events operates off of the 20 KHz Keep

Alive Oscillator.

Upon the occurrence of an event, which is programmed to assert IRQ_N, the 48 MHz Relaxation Oscillator and Ring

Oscillator are enabled. Upon synchronization, the IRQ_N pin shall assert.

After software services the source interrupt(s), it should disable the 48 MHz Relaxation Oscillator and Ring Oscillator

via the Clock Control Register (CLK_CTL) to place the part back in STANDBY.

The following example sequence illustrates the steps for configuring the device to detect an OCS event on the OCS_-

COMP1 pin while in STANDBY.

Software enables the OCS_CMP_INT bit in the Interrupt Enable Register (INT_EN).

Software enables OCS detection, as defined in Section 8.3, "External Over-current Detection", to sample the

OCS_COMP1 pin.

Software disables the 48 MHz Relaxation Oscillator and Ring Oscillator via the Clock Control Register

(CLK_CTL).

An OCS event occurs and is detected on OCS_COMP1.

The Ring Oscillator is enabled and is used to as the device’s operational clock.

The device enables the 48 MHz oscillator and waits about 5 us for the oscillator to stabilize.

The 48 MHz oscillator is stable.

After synchronization is complete, the IRQ_N pin is asserted.

Software detects IRQ_N assertion and services the interrupt.

10. Software disables the 48 MHz Relaxation Oscillator and Ring Oscillator via the Clock Control Register

(CLK_CTL) to place the part back in STANDBY.

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