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UPD360 Arkusz danych(PDF) 104 Page - Microchip Technology |
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UPD360 Arkusz danych(HTML) 104 Page - Microchip Technology |
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104 / 221 page ![]() UPD360 DS00002084C-page 104 2016-2017 Microchip Technology Inc. 9.12.28 VBUS VSAFE0V THRESHOLD REGISTER (VSAFE0V_THR) Note 9-14 The defaults are defined in Table 9-14. APPLICATION NOTE: This register may be dynamically written to by software while the VBUS comparator is enabled, provided the rules for updating defined in the register description are followed. 9.12.29 CFG_SELX MATCH REGISTERS (CFG_SELX_MATCH) Address: 084Eh Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:10 RESERVED RO - 9:0 VSAFE0V Threshold (VSAFE0V_THR) VSAFE0V Threshold register. The lower byte of the threshold must be written before the upper byte. The entire 10-bit threshold is updated when the second write occurs. Note: The units of this register are ~2.44 mV from a 2.5V FS. R/W Note 9-14 TABLE 9-14: VSAFE0V_THR DEFAULTS VSAFE0V_THR VBUS Threshold 1R/9R Divider VALUE VSAFE0V_THR 0.8 0.08 32 Address: x=0: 0850h x=1: 0852h Size: 16 bits Bits Description Type Default 15:0 Configuration Select X Match (CFG_SELX_MATCH) Indicates which configuration select thresholds are matched on the CFG_SELx pin. A match is determined when the measured voltage exceeds the programmed threshold. See Section 9.8.1, "Configuration Selection," on page 81. RO 0h |
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