 |
Zakładka z wyszukiwarką danych komponentów |
|
|
Zakładka z wyszukiwarką danych komponentów |
|
SC3200 Arkusz danych(PDF) 37 Page - Advanced Micro Devices |
|
|
|||||||||||||||||||||||||||||
SC3200 Arkusz danych(HTML) 37 Page - Advanced Micro Devices |
|
|
37 / 447 page  AMD Geode™ SC3200 Processor Data Book 37 Signal Definitions Revision 5.1 AK233 MD30 I/O INT, TS2/5 VIO --- AK243 MD53 I/O INT, TS2/5 VIO --- AK25 VIO PWR --- --- --- AK26 VSS GND --- --- --- AK273 MD21 I/O INT, TS2/5 VIO --- AK283 MD18 I/O INT, TS2/5 VIO --- AK29 CS1# O O2/5 VIO --- AK30 VSS GND --- --- --- AK31 VIO PWR --- --- --- AL1 VSS GND --- --- --- AL2 VIO PWR --- --- --- AL3 TDN I/O WIRE VIO --- AL4 TCK I (PU22.5) INPCI VIO --- AL5 GTEST I (PD22.5) INT VIO --- AL6 VPD5 I INT VIO --- AL7 VPD3 I INT VIO --- AL8 GPIO39 I/O (PU22.5) INPCI, OPCI VIO PMR[14]5 = 0 and PMR[22]5 = 0 SERIRQ I/O INPCI, OPCI PMR[14]5 = 1 and PMR[22]5 = 1 AL9 GPIO36 I/O (PU22.5) INPCI, OPCI VIO PMR[14]5 = 0 and PMR[22]5 = 0 LDRQ# I INPCI PMR[14]5 = 1 and PMR[22]5 = 1 AL10 GPIO33 I/O (PU22.5) INPCI, OPCI VIO PMR[14]5 = 0 and PMR[22]5 = 0 LAD1 I/O (PU22.5) INPCI, OPCI PMR[14]5 = 1 and PMR[22]5 = 1 AL11 GPIO13 I/O (PU22.5) INAB, O8/ 8 VIO PMR[19] = 0 AB2D I/O (PU22.5) INAB, OD8 VIO PMR[19] = 1 AL12 AB1D I/O (PU22.5) INAB, OD8 VIO PMR[23]2 = 0 GPIO1 I/O (PU22.5) INT, O3/5 PMR[23]2 = 1and PMR[13] = 0 IOCS1# O O3/5 PMR[23]2 = 1 and PMR[13] = 1 AL13 SYNC O OAC97 VIO --- CLKSEL3 I (PD100) INSTRP Strap (See Table 3-6 on page 58.) AL14 BIT_CLK I INT VIO FPCI_MON = 0 F_TRDY# O O1/4 FPCI_MON = 1 AL15 GPIO16 I/O (PU22.5) INT, O2/5 VIO PMR[0] = 0 and FPCI_MON = 0 PC_BEEP O O2/5 PMR[0] = 1 = 0 and FPCI_MON = 0 F_DEVSEL# O O2/5 FPCI_MON = 1 Ball No. Signal Name I/O (PU/ PD) Buffer1 Type Power Rail Configuration AL16 GXCLK O O2/5 VIO PMR[23]2 = 0 and PMR[29] = 0 FP_VDD_ON O O1/4 PMR[23]2 = 1 TEST3 O O2/5 PMR[23]2 = 0 and PMR[29] = 1 and AL173 MD57 I/O INT, TS2/5 VIO --- AL183 MD60 I/O INT, TS2/5 VIO --- AL193 MD63 I/O INT, TS2/5 VIO --- AL20 SDCLK2 O O2/5 VIO --- AL213 MD24 I/O INT, TS2/5 VIO --- AL223 MD27 I/O INT, TS2/5 VIO --- AL233 MD31 I/O INT, TS2/5 VIO --- AL243 MD52 I/O INT, TS2/5 VIO --- AL253 MD49 I/O INT, TS2/5 VIO --- AL26 DQM2 O O2/5 VIO --- AL273 MD20 I/O INT, TS2/5 VIO --- AL283 MD17 I/O INT, TS2/5 VIO --- AL293 MD16 I/O INT, TS2/5 VIO --- AL30 VIO PWR --- --- --- AL31 VSS GND --- --- --- 1. For Buffer Type definitions, refer to Table 9-10 "Buffer Types" on page 375. 2. The TFT_PRSNT strap determines the power-on reset (POR) state of PMR[23]. 3. Is back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1, DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3, ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). 4. Is 5V tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). 5. The LPC_ROM strap determines the power-on reset (POR) state of PMR[14] and PMR[22]. Ball No. Signal Name I/O (PU/ PD) Buffer1 Type Power Rail Configuration Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Polish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
