SC3200 datasheet(69/447 Pages) AMD

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AMD Geode™ SC3200 Processor Data Book

Signal Definitions

Revision 5.1

PAR

C10

I/O

Parity. Parity generation is required by all

PCI agents. The master drives PAR for

address- and write-data phases. The target

drives PAR for read-data phases. Parity is

even across AD[31:0] and C/BE[3:0]#.

For address phases, PAR is stable and valid

one PCI clock after the address phase. It has

the same timing as AD[31:0] but is delayed

by one PCI clock.

For data phases, PAR is stable and valid one

PCI clock after either IRDY# is asserted on a

write transaction or after TRDY# is asserted

on a read transaction.

Once PAR is valid, it remains valid until one

PCI clock after the completion of the data

phase. (Also see PERR#.)

D12

FRAME#

I/O

Frame Cycle. Frame is driven by the current

master to indicate the beginning and duration

of an access. FRAME# is asserted to indi-

cate the beginning of a bus transaction.

While FRAME# is asserted, data transfers

continue. FRAME# is de-asserted when the

transaction is in the final data phase.

This signal is internally connected to a pull-

up resistor.

---

IRDY#

I/O

Initiator Ready. IRDY# is asserted to indi-

cate that the bus master is able to complete

the current data phase of the transaction.

IRDY# is used in conjunction with TRDY#. A

data phase is completed on any PCI clock in

which both IRDY# and TRDY# are sampled

as asserted. During a write, IRDY# indicates

that valid data is present on AD[31:0]. During

a read, it indicates that the master is pre-

pared to accept data. Wait cycles are

inserted until both IRDY# and TRDY# are

asserted together.

This signal is internally connected to a pull-

up resistor.

D14

3.4.6

PCI Bus Interface Signals (Continued)

Signal Name

BalL No.

Type

Description

Mux

EBGA

TEPBGA

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