SC3200 datasheet(70/447 Pages) AMD

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AMD Geode™ SC3200 Processor Data Book

Signal Definitions

Revision 5.1

TRDY#

I/O

Target Ready. TRDY# is asserted to indi-

cate that the target agent is able to complete

the current data phase of the transaction.

TRDY# is used in conjunction with IRDY#. A

data phase is complete on any PCI clock in

which both TRDY# and IRDY# are sampled

as asserted. During a read, TRDY# indicates

that valid data is present on AD[31:0]. During

a write, it indicates that the target is prepared

to accept data. Wait cycles are inserted until

both IRDY# and TRDY# are asserted

together.

This signal is internally connected to a pull-

up resistor.

D13

STOP#

I/O

Target Stop. STOP# is asserted to indicate

that the current target is requesting that the

master stop the current transaction. This sig-

nal is used with DEVSEL# to indicate retry,

disconnect, or target abort. If STOP# is sam-

pled active by the master, FRAME# is de-

asserted and the cycle is stopped within

three PCI clock cycles. As an input, STOP#

can be asserted in the following cases:

If a PCI master tries to access memory

that has been locked by another master.

This condition is detected if FRAME#

and LOCK# are asserted during an

address phase.

If the PCI write buffers are full or if a pre-

viously buffered cycle has not com-

pleted.

On read cycles that cross cache line

boundaries. This is conditional based

upon the programming of GX1 module’s

PCI

Configuration

Index

41h[1].

This signal is internally connected to a pull-

up resistor.

D15

3.4.6

PCI Bus Interface Signals (Continued)

Signal Name

BalL No.

Type

Description

Mux

EBGA

TEPBGA

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