SC3200 datasheet(71/447 Pages) AMD

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AMD Geode™ SC3200 Processor Data Book

Signal Definitions

Revision 5.1

LOCK#

I/O

Lock Operation. LOCK# indicates an atomic

operation that may require multiple transac-

tions to complete. When LOCK# is asserted,

non-exclusive transactions may proceed to

an address that is not currently locked (at

least 16 bytes must be locked). A grant to

start a transaction on PCI does not guaran-

tee control of LOCK#. Control of LOCK# is

obtained under its own protocol in conjunc-

tion with GNT#.

It is possible for different agents to use PCI

while a single master retains ownership of

LOCK#. The arbiter can implement a com-

plete system lock. In this mode, if LOCK# is

active, no other master can gain access to

the system until the LOCK# is de-asserted.

This signal is internally connected to a pull-

up resistor.

---

DEVSEL#

I/O

Device Select. DEVSEL# indicates that the

driving device has decoded its address as

the target of the current access. As an input,

DEVSEL# indicates whether any device on

the bus has been selected. DEVSEL# is also

driven by any agent that has the ability to

accept cycles on a subtractive decode basis.

As a master, if no DEVSEL# is detected

within and up to the subtractive decode

clock, a master abort cycle is initiated (except

for special cycles which do not expect a

DEVSEL# returned).

This signal is internally connected to a pull-

up resistor.

BHE#

PERR#

I/O

Parity Error. PERR# is used for reporting

data parity errors during all PCI transactions

except a Special Cycle. The PERR# line is

driven two PCI clocks after the data in which

the error was detected. This is one PCI clock

after the PAR that is attached to the data.

The minimum duration of PERR# is one PCI

clock for each data phase in which a data

parity error is detected. PERR# must be

driven high for one PCI clock before being

placed in TRI-STATE. A target asserts

PERR# on write cycles if it has claimed the

cycle with DEVSEL#. The master asserts

PERR# on read cycles.

This signal is internally connected to a pull-

up resistor.

---

3.4.6

PCI Bus Interface Signals (Continued)

Signal Name

BalL No.

Type

Description

Mux

EBGA

TEPBGA

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