STM8S103F2 datasheet(46/121 Pages) STMICROELECTRONICS

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Option byte

STM8S103F2 STM8S103F3 STM8S103K3

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DocID15441 Rev 14

Table 12. Option byte description

Option byte no.

Description

OPT0

ROP[7:0] Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

Note: Refer to the family reference manual (RM0016) section on

Flash/EEPROM memory readout protection for details.

OPT1

UBC[7:0] User boot code area

0x00: no UBC, no write-protection

0x01: Page 0 defined as UBC, memory write-protected

Page 0 and 1 contain the interrupt vectors.

...

0x7F: Pages 0 to 126 defined as UBC, memory write-protected

Other values: Pages 0 to 127 defined as UBC, memory write-protected

Note: Refer to the family reference manual (RM0016) section on Flash write

protection for more details.

OPT2

AFR[7:0]

Refer to the following section for alternate function remapping descriptions of

bits [7:2] and [1:0] respectively.

OPT3

HSITRIM: High speed internal clock trimming register size

0: 3-bit trimming supported in CLK_HSITRIMR register

1: 4-bit trimming supported in CLK_HSITRIMR register

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

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