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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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IMX8MPCEC Arkusz danych(PDF) 40 Page - NXP Semiconductors |
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IMX8MPCEC Arkusz danych(HTML) 40 Page - NXP Semiconductors |
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40 / 111 page  i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021 40 NXP Semiconductors Electrical characteristics 3.5.2 DDR I/O AC electrical characteristics The DDR I/O pads support LPDDR 4 and DDR4 operational modes. The DDR Memory Controller (DDRMC) is compliant with JEDEC-compliant SDRAMs. DDRMC operation is contingent upon the board’s DDR design adherence to the DDR design and layout requirements stated in the hardware development guide for the i.MX 8M Plus application processor. 3.5.3 LVDS I/O AC Parameters The differential output transition time waveform is shown in Figure 9. Table 30. Maximum frequency of operation for output Parameter Maximum Frequency (MHz) VDD = 1.8 V VDD = 3.3 V dse[2:0] sre[1:0] Driver type CL = 10 pF CL = 20 pF CL = 10 pF CL = 20 pF 00X 0X 1x Slow Slew 150 80 120 65 00X 1X 1x Fast Slew 150 80 120 65 10X 0X 2x Slow Slew 160 90 150 80 10X 1X 2x Fast Slew 160 90 150 80 01X 0X 4x Slow Slew 200 100 180 90 01X 1X 4x Fast Slew 200 100 180 90 11X 0X 6x Slow Slew 250 130 200 100 11X 1X 6x Fast Slew 250 130 200 100 |
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